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Oregon State researchers showcase advances in semiconductors

Researchers from Oregon State University are presenting results in semiconductor advancements at the 2013 Symposia on VLSI Technology and Circuits in Kyoto, Japan on June 11-14, 2013. A highlight among presentations is a new digital PLL architecture using a novel scrambling time-to-digital converter to overcome jitter accumulation that plagues all digital PLLs. Other papers describe energy efficient architectures to perform analog-to-digital conversion and clock and data recovery.


A 4.1mW, 12-bit ENOB, 5MHz BW, VCO-Based ADC with On-Chip Deterministic Digital Background Calibration in 90nm CMOS
S. Rao, K. Reddy, B. Young and P.K. Hanumolu, Oregon State University
A deterministic digital background calibration technique to correct non-linearity in VCO-based ADCs is presented. Implemented in 90nm CMOS process, on-chip calibration improves SFDR of the prototype ADC from 46dB to more than 83dB. The ADC consumes 4.1mW power and achieves 73.9dB SNDR in 5MHz signal bandwidth.

A 2.5GHz 5.4mW 1-to-2048 Digital Clock Multiplier Using a Scrambling TDC
R.K. Nandwana, S.Saxena, A. Elshazly, K. Mayaram and P.K. Hanumolu, Oregon State University
A scrambling TDC is proposed to mitigate dithering jitter accumulation in clock multipliers with low reference frequencies. Fabricated in a 90nm CMOS process, the prototype operates with a 1.25MHz reference clock and generates 160MHz and 2.56GHz output clocks with a long-term absolute jitter of 2.7ps-rms and 6.28ps-rms, respectively.

A 5Gb/s 2.6mW/Gb/s Reference-less Half-Rate PRPLL-Based Digital CDR, G. Shu, S. Saxena, W.-S. Choi, M. Talegaonkar, R. Inti, A. Elshazly, B. Young and P.K. Hanumolu, Oregon State University
A reference-less half-rate digital CDR implements proportional control in phase domain with a phase-rotating PLL (PRPLL) which decouples jitter transfer (JTRAN) bandwidth and jitter tolerance (JTOL) corner frequency, eliminates jitter peaking, and removes JTRAN dependence on phase detector gain. Fabricated in a 90nm CMOS process, the prototype CDR achieves 2MHz JTRAN, 16MHz JTOL, and consumes 13.1mW from 1V supply at 5Gb/s with BER<10-12.

A Fast Power-on 2.2Gb/s Burst-Mode Digital CDR with Programmable Input Jitter Filtering
W.-S. Choi, T. Anand, G. Shu and P.K. Hanumolu, Oregon State University
A digital burst-mode CDR employs feed-forward data edge injection and a digital feedback loop to achieve instantaneous phase locking, data-rate tracking, and input jitter filtering. Fabricated in a 90nm CMOS process, the prototype receiver achieves instantaneous locking on the very first data edge and consumes 6.1mW at 2.2Gb/s. By controlling the edge injection rate, the proposed architecture allows variable JTRAN bandwidth from 5MHz to 40MHz.

A 75.9dB-SNDR 2.96mW 29fJ/Conv-Step Ringamp-Only Pipelined ADC
B. Hershberg** and U.-K. Moon*, *Oregon State University, USA and **Imec, Belgium
A high resolution pipelined ADC that performs precision amplification using only ring amplifiers is presented. Several enabling techniques are introduced, namely parallelization via the use of Composite Ring Amplifier Blocks and a new ringamp topology designed for high-precision use. The 15b ADC achieves 75.9 dB SNDR and 91.4 dB SFDR at 1.2 V supply and 20 Msps conversion rate. Total power consumption is 2.96 mW, resulting in a Figure-of-Merit of 29 fJ/c-step.

A 70MS/s 69.3dB SNDR 38.2fJ/Conversion-Step Time-Based Pipelined ADC
T. Oh, H. Venkatram and U.-K. Moon, Oregon State University
A Nyquist ADC with time-based pipelined architecture is proposed. The proposed hybrid pipeline stage, incorporating time- domain amplification based on a charge pump, enables power efficient analog to digital conversion. The proposed ADC also adopts a minimalist switched amplifier with 24dB open-loop dc gain in the first stage MDAC that is based on a new V-T operation, instead of a conventional high gainamplifier. The measured results of the prototype ADC implemented in a 0.13μm CMOS demonstrate peak SNDR of 69.3dB at 6.38mW power, with a near rail-to-rail 1MHz input of 2.4Vpp at 70MHz sampling frequency and 1.3V supply. This results in 38.2fJ/conversion-step FOM.