OREGON STATE UNIVERSITY

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Found 124 results
Filters: Author is Temes, Gabor C.  [Clear All Filters]
2013
Chen, C. - H., Y. Zhang, and G. C. Temes, "Accuracy-enhanced switched-capacitor stages using low-gain opamps", Electronics Letters, vol. 49, issue 1, pp. 22 - 23, 01/2013.
Chen, C. - H., Y. Jung, J. L. Ceballos, and G. C. Temes, "Multi-step extended-counting analogue-to-digital converters", Electronics Letters, vol. 49, issue 1, pp. 30 - 31, 01/2013.
Chen, C. - H., Y. Zhang, G. C. Temes, and J. L. Ceballos, "Noise-shaping SAR ADC using three capacitors", Electronics Letters, vol. 49, issue 3, pp. 182 - 184, 01/2013.
He, T., J. L. Ceballos, G. C. Temes, C. - H. Chen, Y. Zhang, and Y. Jung, "Two-step incremental analogue-to-digital converter", Electronics Letters, vol. 49, issue 4, pp. 250 - 251, 02/2013.
2012
Wang, T., W. Li, H. Yoshizawa, M. Aslan, and G. C. Temes, "A 101 dB DR 1.1 mW audio delta-sigma modulator with direct-charge-transfer adder and noise shaping enhancement", IEEE Asian Solid State Circuits Conference (A-SSCC), Kobe, Japan, IEEE, pp. 249 - 252, 11/2012.
Chen, C-H., J. Crop, J. Chae, P. Y. Chiang, and G. C. Temes, "A 12-bit 7 µW/channel 1 kHz/channel incremental ADC for biosensor interface circuits", 2012 IEEE International Symposium on Circuits and Systems - ISCAS 2012, Seoul, Korea (South), IEEE, pp. 2969 - 2972, 05/2012.
Zanbaghi, R., S. Saxena, G. C. Temes, and T. S. Fiez, "A 75-dB SNDR, 5-MHz Bandwidth Stage-Shared 2-2 MASH ΔΣ Modulator Dissipating 16 mW Power", IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 59, issue 8, pp. 1614 - 1625, 08/2012.
Tong, T., W. Yu, P K. Hanumolu, and G. C. Temes, "Calibration technique for SAR analog-to-digital converters", 2012 IEEE International Symposium on Circuits and Systems - ISCAS 2012, Seoul, Korea (South), IEEE, pp. 2993 - 2996, 05/2012.
Meng, X., G. C. Temes, and T. Wang, "Charge compensation technique for switched-capacitor circuits", Electronics Letters, vol. 48, issue 16, pp. 988 - 990, 08/2012.
Yu, W., and G. C. Temes, "Digital DAC calibration technique for and incremental modulators", Electronics Letters, vol. 48, issue 13, pp. 754, 06/2012.
Li, W., T. Wang, and G. C. Temes, "Digital foreground calibration methods for SAR ADCs", 2012 IEEE International Symposium on Circuits and Systems - ISCAS 2012, Seoul, Korea (South), IEEE, pp. 1054 - 1057, 05/2012.
Jung, Y., S. Lee, C. - H. Chen, and G. C. Temes, "Double noise coupling analogue-to-digital converter", Electronics Letters, vol. 48, issue 10, pp. 557, 05/2012.
Cao, J., R. Raich, G. C. Temes, and G. Cauwenberghs, "Multi-channel mixed-signal noise source with applications to stochastic equalization", 2012 IEEE International Symposium on Circuits and Systems - ISCAS 2012, Seoul, Korea (South), IEEE, pp. 2497 - 2500, 05/2012.
Tong, T., P K. Hanumolu, and G. C. Temes, "A semi-synchronous SAR ADC", Analog Integrated Circuits and Signal Processing, vol. 71, issue 3, pp. 407 - 410, 06/2012.
Li, W., T. Wang, J. Cao, and G. C. Temes, "Teraohm on-chip resistance realisation using switched capacitor topologies", Electronics Letters, vol. 48, issue 11, pp. 623, 05/2012.
2011
Zanbaghi, R., S. Saxena, G. C. Temes, and T. S. Fiez, "A 75dB SNDR, 10MHz conversion bandwidth stage-shared 2-2 MASH ΔΣ modulator dissipating 9mW", 2011 IEEE Custom Integrated Circuits Conference (CICC), San Jose, CA, IEEE, pp. 1 - 4, 10/2011.
Wang, Y., P K. Hanumolu, and G. C. Temes, "Design Techniques for Wideband Discrete-Time Delta-Sigma ADCs With Extra Loop Delay", IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 58, issue 7, pp. 1518 - 1530, 07/2011.
Lee, S., J. Chae, M. Aniya, S. Takeuchi, K. Hamashita, P K. Hanumolu, and G. C. Temes, "A double-sampled low-distortion cascade ΔΣ modulator with an adder/integrator for WLAN application", 2011 IEEE Custom Integrated Circuits Conference (CICC), San Jose, CA, IEEE, pp. 1 - 4, 09/2011.
Yoshizawa, H., T. Yabe, and G. C. Temes, "High-precision switched-capacitor integrator using low-gain opamp", Electronics Letters, vol. 47, issue 5, pp. 315 - 316 , 03/2011.
Jung, Y., S. Lee, J. Chae, and G. C. Temes, "Low-power and low-offset comparator using latch load", Electronics Letters, vol. 47, issue 3, pp. 167 - 168 , 03/2011.
2010
Chae, J., S. Lee, M. Aniya, S. Takeuchi, K. Hamashita, P K. Hanumolu, and G. C. Temes, "A 63 dB 16 mW 20 MHz BW double-sampled ΔΣs analog-to-digital converter with an embedded-adder quantizer", 2010 IEEE Custom Integrated Circuits Conference 2010, San Jose, CA, IEEE, pp. 1 - 4, 09/2010.
Yu, W., M. Aslan, and G. C. Temes, "82 dB SNDR 20-channel incremental ADC with optimal decimation filter and digital correction", 2010 IEEE Custom Integrated Circuits Conference - CICC, San Jose, CA, IEEE, pp. 1 - 4, 09/2010.
Chae, J., and G. C. Temes, "Comparator-based buffer with resistive error correction", Electronics Letters, vol. 46, issue 17, pp. 1188 - 1190 , 08/2010.
Wang, Y., and G. C. Temes, "Design techniques for discrete-time delta-sigma ADCs with extra loop delay", Proceedings of 2010 IEEE International Symposium on Circuits and Systems, Paris, France, IEEE, pp. 2159 - 2162, 06/2010.
Lin, J., W. Yu, and G. C. Temes, "Energy-efficient time-interleaved and pipelined SAR ADCs", Proceedings of 2010 IEEE International Symposium on Circuits and Systems, Paris, France, IEEE, pp. 1452 - 1455, 06/2010.

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