OREGON STATE UNIVERSITY

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Biblio

Found 13 results
Filters: Author is Babakhani, Aydin  [Clear All Filters]
2012
Sadhu, B., M. A. Ferriss, J-O. Plouchart, A. Natarajan, A. Rylyakov, A. Valdes-Garcia, B. D. Parker, S. Reynolds, A. Babakhani, S. Yaldiz, et al., "A 21.8–27.5GHz PLL in 32nm SOI using Gm linearization to achieve −130dBc/Hz phase noise at 10MHz offset from a 22GHz carrier", IEEE Radio Frequency Integrated Circuits Symposium (RFIC), Montreal, QC, Canada, IEEE, pp. 75 - 78, 06/2012.
Plouchart, J. - O., M. A. Ferriss, A. Natarajan, A. Valdes-Garcia, B. Sadhu, A. Rylyakov, B. Parker, M. Beakes, A. Babakhani, S. Yaldiz, et al., "A 23.5GHz PLL with an adaptively biased VCO in 32nm SOI-CMOS", IEEE Custom Integrated Circuits Conference - CICC 2012, San Jose, CA, IEEE, pp. 1 - 4, 09/2012.
Plouchart, J. - O., M. A. Ferriss, A. Natarajan, A. Valdes-Garcia, B. Sadhu, A. Rylyakov, B. Parker, M. Beakes, A. Babakhani, S. Yaldiz, et al., "A 23.5GHz PLL with an adaptively biased VCO in 32nm SOI-CMOS", IEEE Custom Integrated Circuits Conference - CICC 2012, San Jose, CA, IEEE, pp. 1 - 4, 09/2012.
Ferriss, M. A., J-O. Plouchart, A. Natarajan, A. Rylyakov, B. Parker, A. Babakhani, S. Yaldiz, B. Sadhu, A. Valdes-Garcia, J. Tierno, et al., "An integral path self-calibration scheme for a 20.1–26.7GHz dual-loop PLL in 32nm SOI CMOS", 2012 IEEE Symposium on VLSI Circuits2012 Symposium on VLSI Circuits (VLSIC), Honolulu, HI, IEEE, pp. 176 - 177, 06/2012.
2008
Jeon, S., Y-J. Wang, H. Wang, F. Bohn, A. Natarajan, A. Babakhani, and A. Hajimiri, "A Scalable 6-to-18 GHz Concurrent Dual-Band Quad-Beam Phased-Array Receiver in CMOS", IEEE Journal of Solid-State Circuits, vol. 43, issue 12, pp. 2660 - 2673, 12/2008.
Jeon, S., Y-J. Wang, H. Wang, F. Bohn, A. Natarajan, A. Babakhani, and A. Hajimiri, "A Scalable 6-to-18GHz Concurrent Dual-Band Quad-Beam Phased-Array Receiver in CMOS", IEEE Solid-State Circuits Conference (ISSCC), San Francisco, CA, IEEE, pp. 186 - 605, 02/2008.
Wang, H., S. Jeon, Y-J. Wang, F. Bohn, A. Natarajan, A. Babakhani, and A. Hajimiri, "A tunable concurrent 6-to-18GHz phased-array system in CMOS", IEEE MTT-S International Microwave Symposium Digest - MTT 2008, Atlanta, GA, IEEE, pp. 687 - 690, 06/2008.
2006
Babakhani, A., X. Guan, A. Komijani, A. Natarajan, and A. Hajimiri, "A 77GHz 4-Element Phased Array Receiver with On-Chip Dipole Antennas in Silicon", IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, IEEE, pp. 629 - 638, 02/2006.
Babakhani, A., X. Guan, A. Komijani, A. Natarajan, and A. Hajimiri, "A 77-GHz Phased-Array Transceiver With On-Chip Antennas in Silicon: Receiver and Antennas", IEEE Journal of Solid-State Circuits, vol. 41, issue 12, pp. 2795 - 2806, 12/2006.
Natarajan, A., A. Komijani, X. Guan, A. Babakhani, and A. Hajimiri, "A 77-GHz Phased-Array Transceiver With On-Chip Antennas in Silicon: Transmitter and Local LO-Path Phase Shifting", IEEE Journal of Solid-State Circuits, vol. 41, issue 12, pp. 2807 - 2819, 12/2006.
Natarajan, A., A. Komijani, X. Guan, A. Babakhani, Y. Wang, and A. Hajimiri, "A 77GHz Phased-Array Transmitter with Local LO-Path Phase-Shifting in Silicon", IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, IEEE, pp. 639 - 648, 02/2006.