OREGON STATE UNIVERSITY

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Biblio

Found 6 results
Filters: Author is Rylyakov, Alexander  [Clear All Filters]
2012
Sadhu, B., M. A. Ferriss, J-O. Plouchart, A. Natarajan, A. Rylyakov, A. Valdes-Garcia, B. D. Parker, S. Reynolds, A. Babakhani, S. Yaldiz, et al., "A 21.8–27.5GHz PLL in 32nm SOI using Gm linearization to achieve −130dBc/Hz phase noise at 10MHz offset from a 22GHz carrier", IEEE Radio Frequency Integrated Circuits Symposium (RFIC), Montreal, QC, Canada, IEEE, pp. 75 - 78, 06/2012.
Plouchart, J. - O., M. A. Ferriss, A. Natarajan, A. Valdes-Garcia, B. Sadhu, A. Rylyakov, B. Parker, M. Beakes, A. Babakhani, S. Yaldiz, et al., "A 23.5GHz PLL with an adaptively biased VCO in 32nm SOI-CMOS", IEEE Custom Integrated Circuits Conference - CICC 2012, San Jose, CA, IEEE, pp. 1 - 4, 09/2012.
Plouchart, J. - O., M. A. Ferriss, A. Natarajan, A. Valdes-Garcia, B. Sadhu, A. Rylyakov, B. Parker, M. Beakes, A. Babakhani, S. Yaldiz, et al., "A 23.5GHz PLL with an adaptively biased VCO in 32nm SOI-CMOS", IEEE Custom Integrated Circuits Conference - CICC 2012, San Jose, CA, IEEE, pp. 1 - 4, 09/2012.
Ferriss, M. A., J-O. Plouchart, A. Natarajan, A. Rylyakov, B. Parker, A. Babakhani, S. Yaldiz, B. Sadhu, A. Valdes-Garcia, J. Tierno, et al., "An integral path self-calibration scheme for a 20.1–26.7GHz dual-loop PLL in 32nm SOI CMOS", 2012 IEEE Symposium on VLSI Circuits2012 Symposium on VLSI Circuits (VLSIC), Honolulu, HI, IEEE, pp. 176 - 177, 06/2012.