OREGON STATE UNIVERSITY

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Biblio

Found 8 results
Filters: Author is Kwon, Sunwoo  [Clear All Filters]
2010
Young, B., S. Kwon, A. Elshazly, and P K. Hanumolu, "A 2.4ps resolution 2.1mW second-order noise-shaped time-to-digital converter with 3.2ns range in 1MHz bandwidth", 2010 IEEE Custom Integrated Circuits Conference - CICC, San Jose, CA, IEEE, pp. 1 - 4, 09/2010.
2009
Kwon, S., P K. Hanumolu, S-H. Kim, S-N. Lee, S-B. You, H-J. Park, J-W. Kim, and U. Moon, "An 11mW 100MHz 16X-OSR 64dB-SNDR hybrid CT/DT ΔΣ ADC with relaxed DEM timing", 2009 IEEE Custom Integrated Circuits Conference (CICC), San Jose, CA, IEEE, pp. 171 - 174, 09/2009.
Musah, T., S. Kwon, H. Lakdawala, K. Soumyanath, and U. Moon, "A 630μW zero-crossing-based ΔΣ ADC using switched-resistor current sources in 45nm CMOS", 2009 IEEE Custom Integrated Circuits Conference (CICC), San Jose, CA, IEEE, pp. 1 - 4, 09/2009.
Maghari, N., S. Kwon, and U. Moon, "74 dB SNDR Multi-Loop Sturdy-MASH Delta-Sigma Modulator Using 35 dB Open-Loop Opamp Gain", IEEE Journal of Solid-State Circuits, vol. 44, issue 8, pp. 2212 - 2221, 08/2009.
Gubbins, D., S. Kwon, B. Lee, P K. Hanumolu, and U. Moon, "A continuous-time input pipeline ADC with inherent anti-alias filtering", 2009 IEEE Custom Integrated Circuits Conference (CICC), San Jose, CA, IEEE, pp. 275 - 278, 09/2009.
2008
Maghari, N., S. Kwon, and U. Moon, "74dB SNDR multi-loop sturdy-MASH delta-sigma modulator using 35dB opamp gain", IEEE Custom Integrated Circuits Conference - CICC 2008, San Jose, CA, IEEE, pp. 101 - 104, 09/2008.
Kim, M G., V. Kratyuk, P K. Hanumolu, G-C. Ahn, S. Kwon, and U. Moon, "An 8mW 10b 50MS/s pipelined ADC using 25dB opamp", 2008 IEEE Asian Solid-State Circuits Conference (A-SSCC), Fukuoka, Japan, IEEE, pp. 49 - 52, 11/2008.
2007
Kwon, S., and U. Moon, "A High-Speed Delta-Sigma Modulator with Relaxed DEM Timing Requirement", 2007 IEEE International Symposium on Circuits and Systems, New Orleans, LA, IEEE, pp. 733 - 736, 05/2007.