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Found 16 results
Hu, K., L. Wu, and P. Y. Chiang, "A Comparative Study of 20-Gb/s NRZ and Duobinary Signaling Using Statistical Analysis", IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 20, issue 7, pp. 1336 - 1341, 07/2012.
Jiang, T., P. Y. Chiang, and K. Hu, "A low-power, capacitively-divided, ring oscillator with digitally adjustable voltage swing", 2012 International Symposium on VLSI Design, Automation and Test (VLSI-DAT), Hsinchu, Taiwan, IEEE, pp. 1 - 4, 04/2012.
Hu, K., T. Jiang, S. Palermo, and P. Y. Chiang, "Low-power 8Gb/s near-threshold serial link receivers using super-harmonic injection locking in 65nm CMOS", IEEE Custom Integrated Circuits Conference - CICC 2011, San Jose, CA, IEEE, pp. 1 - 4, 09/2011.
Hu, C., R. Khanna, J. Nejedlo, K. Hu, H. Liu, and P. Y. Chiang, "A 90 nm-CMOS, 500 Mbps, 3–5 GHz Fully-Integrated IR-UWB Transceiver With Multipath Equalization Using Pulse Injection-Locking for Receiver Phase Synchronization", IEEE Journal of Solid-State Circuits, vol. 46, issue 5, pp. 1076 - 1088, 05/2011.
Hu, K., T. Jiang, and P. Y. Chiang, "Comparison of on-die global clock distribution methods for parallel serial links", IEEE International Symposium on Circuits and Systems - ISCAS 2009, Taipei, Taiwan, IEEE, pp. 1843 - 1846, 05/2009.