OREGON STATE UNIVERSITY

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Biblio

Found 7 results
Filters: Author is Postman, Jacob  [Clear All Filters]
2012
Pawlowski, R., E. Krimer, J. Crop, J. Postman, N. Moezzi-Madani, M. Erez, and P. Y. Chiang, "A 530mV 10-lane SIMD processor with variation resiliency in 45nm SOI", 2012 IEEE International Solid- State Circuits Conference - (ISSCC, San Francisco, CA, IEEE, pp. 492 - 494, 02/2012.
Xia, L., J. Wang, W. Beattie, J. Postman, and P. Y. Chiang, "Sub-2-ps, Static Phase Error Calibration Technique Incorporating Measurement Uncertainty Cancellation for Multi-Gigahertz Time-Interleaved T/H Circuits", IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 59, issue 2, pp. 276 - 284, 02/2012.
Postman, J., and P. Y. Chiang, "A Survey Addressing On-Chip Interconnect: Energy and Reliability Considerations", ISRN Electronics, vol. 2012891543625, issue 424170, pp. 1 - 9, 2012.
Postman, J., T. Krishna, C. Edmonds, L-S. Peh, and P. Y. Chiang, "SWIFT: A Low-Power Network-On-Chip Implementing the Token Flow Control Router Architecture With Swing-Reduced Interconnects", IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. PP, issue 99, pp. 1 - 1, 08/2012.
2011
Postman, J., and P. Y. Chiang, "Energy-efficient transceiver circuits for short-range on-chip interconnects", IEEE Custom Integrated Circuits Conference - CICC 2011, San Jose, CA, IEEE, pp. 1 - 4, 09/2011.
2010
Krishna, T., J. Postman, C. Edmonds, L-S. Peh, and P. Y. Chiang, "SWIFT: A SWing-Reduced Interconnect for a Token-Based Network-on-Chip in 90nm CMOS", 2010 IEEE International Conference on Computer Design (ICCD 2010), Amsterdam, Netherlands, IEEE, pp. 439 - 446, 10/2010.