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Filters: Author is Pawlowski, Robert  [Clear All Filters]
Pawlowski, R., E. Krimer, J. Crop, J. Postman, N. Moezzi-Madani, M. Erez, and P. Y. Chiang, "A 530mV 10-lane SIMD processor with variation resiliency in 45nm SOI", 2012 IEEE International Solid- State Circuits Conference - (ISSCC, San Francisco, CA, IEEE, pp. 492 - 494, 02/2012.
Crop, J., R. Pawlowski, and P. Y. Chiang, "Regaining throughput using completion detection for error-resilient, near-threshold logic", Proceedings of the 49th Annual Design Automation Conference - DAC '12, San Francisco, CA, ACM Press, pp. 974-979, 06/2012.
Crop, J., S. Fairbanks, R. Pawlowski, and P. Y. Chiang, "150mV sub-threshold Asynchronous multiplier for low-power sensor applications", 2010 International Symposium on VLSI Design, Automation and Test (VLSI-DAT), Hsin Chu, Taiwan, IEEE, pp. 254 - 257, 04/2010.
Krimer, E., R. Pawlowski, M. Erez, and P. Y. Chiang, "Synctium: a Near-Threshold Stream Processor for Energy-Constrained Parallel Applications", IEEE Computer Architecture Letters, vol. 9, issue 1, pp. 21 - 24, 01/2010.