Biblio

Found 11 results

2012
Krimer, E., P. Y. Chiang, and M. Erez, "Lane decoupling for improving the timing-error resiliency of wide-SIMD architectures", Proceedings of the 39th Annual International Symposium on Computer Architecture , vol. 40, issue 3, Portland, OR, pp. 237-248 , 06/2012. Abstract
Pawlowski, R., E. Krimer, J. Crop, J. Postman, N. Moezzi-Madani, M. Erez, and P. Y. Chiang, "A 530mV 10-lane SIMD processor with variation resiliency in 45nm SOI", 2012 IEEE International Solid- State Circuits Conference - (ISSCC, San Francisco, CA, IEEE, pp. 492 - 494, 02/2012. Abstract
2011
, , , 10/2011.
, , , 07/2011.
2010
, , , 01/2010.
Krimer, E., R. Pawlowski, M. Erez, and P. Y. Chiang, "Synctium: a Near-Threshold Stream Processor for Energy-Constrained Parallel Applications", IEEE Computer Architecture Letters, vol. 9, issue 1, pp. 21 - 24, 01/2010. Abstract
2009
, , , 07/2009.
2008
, , , 08/2008.
Krishna, T., A. Kumar, P. Y. Chiang, M. Erez, and L. - S. Peh, "NoC with Near-Ideal Express Virtual Channels Using Global-Line Communication", IEEE Symposium on High Performance Interconnects, Stanford, CA, IEEE, pp. 11 - 20, 08/2008. Abstract