OREGON STATE UNIVERSITY

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Biblio

Found 13 results
Filters: Author is Inti, Rajesh  [Clear All Filters]
2012
Elshazly, A., R. Inti, B. Young, and P K. Hanumolu, "A 1.5GHz 890μW digital MDLL with 400fsrms integrated jitter, −55.6dBc reference spur and 20fs/mV supply-noise sensitivity using 1b TDC", 2012 IEEE International Solid- State Circuits Conference - (ISSCC), San Francisco, CA, IEEE, pp. 242 - 244, 02/2012.
Reddy, K., S. Rao, R. Inti, B. Young, A. Elshazly, M. Talegaonkar, and P K. Hanumolu, "A 16mW 78dB-SNDR 10MHz-BW CT-ΔΣ ADC using residue-cancelling VCO-based quantizer", 2012 IEEE International Solid- State Circuits Conference - (ISSCC), San Francisco, CA, IEEE, pp. 152 - 154, 02/2012.
2011
Elshazly, A., R. Inti, W. Yin, B. Young, and P K. Hanumolu, "A 0.4-to-3 GHz Digital PLL With PVT Insensitive Supply Noise Cancellation Using Deterministic Background Calibration", IEEE Journal of Solid-State Circuits, vol. 46, issue 12, pp. 2759 - 2771, 12/2011.
Elshazly, A., R. Inti, W. Yin, B. Young, and P K. Hanumolu, "A 0.4-to-3GHz digital PLL with supply-noise cancellation using deterministic background calibration", 2011 IEEE International Solid- State Circuits Conference - (ISSCC), San Francisco, CA, IEEE, pp. 92 - 94, 02/2011.
Inti, R., W. Yin, A. Elshazly, N. Sasidhar, and P K. Hanumolu, "A 0.5-to-2.5 Gb/s Reference-Less Half-Rate Digital CDR With Unlimited Frequency Acquisition Range and Improved Input Duty-Cycle Error Tolerance", IEEE Journal of Solid-State Circuits, vol. 46, issue 12, pp. 3150 - 3162, 12/2011.
Inti, R., W. Yin, A. Elshazly, N. Sasidhar, and P K. Hanumolu, "A 0.5-to-2.5Gb/s reference-less half-rate digital CDR with unlimited frequency acquisition range and improved input duty-cycle error tolerance", 2011 IEEE International Solid-State Circuits Conference - (ISSCC), San Francisco, CA, IEEE, pp. 438 - 450, 02/2011.
Yin, W., R. Inti, A. Elshazly, B. Young, and P K. Hanumolu, "A 0.7-to-3.5 GHz 0.6-to-2.8 mW Highly Digital Phase-Locked Loop With Bandwidth Tracking", IEEE Journal of Solid-State Circuits, vol. 46, issue 8, pp. 1870 - 1880, 08/2011.
Talegaonkar, M., R. Inti, and P K. Hanumolu, "Digital clock and data recovery circuit design: Challenges and tradeoffs", 2011 IEEE Custom Integrated Circuits Conference (CICC), San Jose, CA, IEEE, pp. 1 - 8, 09/2011.
Inti, R., A. Elshazly, B. Young, W. Yin, M. Kossel, T. Toifl, and P K. Hanumolu, "A highly digital 0.5-to-4Gb/s 1.9mW/Gb/s serial-link transceiver using current-recycling in 90nm CMOS", 2011 IEEE International Solid-State Circuits Conference - (ISSCC), San Francisco, CA, IEEE, pp. 152 - 154, 02/2011.
Yin, W., R. Inti, A. Elshazly, M. Talegaonkar, B. Young, and P K. Hanumolu, "A TDC-Less 7 mW 2.5 Gb/s Digital CDR With Linear Loop Dynamics and Offset-Free Data Recovery", IEEE Journal of Solid-State Circuits, vol. 46, issue 12, pp. 3163 - 3173, 12/2011.
Yin, W., R. Inti, A. Elshazly, and P K. Hanumolu, "A TDC-less 7mW 2.5Gb/s digital CDR with linear loop dynamics and offset-free data recovery", 2011 IEEE International Solid- State Circuits Conference - (ISSCC), San Francisco, CA, IEEE, pp. 440 - 442, 02/2011.
2010
Yin, W., R. Inti, and P K. Hanumolu, "A 1.6mW 1.6ps-rms-jitter 2.5GHz digital PLL with 0.7-to-3.5GHz frequency range in 90nm CMOS", 2010 IEEE Custom Integrated Circuits Conference - CICC 2010, San Jose, CA, IEEE, pp. 1 - 4, 09/2010.
Venkatram, H., R. Inti, and U. Moon, "Least Mean Square calibration method for VCO non-linearity", 2010 International Conference on Microelectronics (ICM), Cairo, Egypt, IEEE, pp. 1 - 4, 12/2010.