OREGON STATE UNIVERSITY

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Biblio

Found 91 results
Filters: Author is Hanumolu, Pavan Kumar  [Clear All Filters]
2013
Zanbaghi, R., P K. Hanumolu, and T. S. Fiez, "An 80-dB DR, 7.2-MHz Bandwidth Single Opamp Biquad Based Delta Sigma Modulator Dissipating 13.7-mW ", IEEE Journal of Solid-State Circuits, vol. 48, issue 2, pp. 487 - 501, 02/2013.
2012
Asl, S Z., S. Saxena, P K. Hanumolu, K. Mayaram, and T. S. Fiez, "A 12.5-bit 4 MHz 13.8 mW MASH Delta-Sigma Modulator With Multirated VCO-Based ADC", IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 59, issue 8, pp. 1604 - 1613, 08/2012.
Elshazly, A., S. Rao, B. Young, and P K. Hanumolu, "A 13b 315fsrms 2mW 500MS/s 1MHz bandwidth highly digital time-to-digital converter using switched ring oscillators", 2012 IEEE International Solid-State Circuits Conference - (ISSCC), San Francisco, CA, IEEE, pp. 464 - 466, 02/2012.
Elshazly, A., R. Inti, B. Young, and P K. Hanumolu, "A 1.5GHz 890μW digital MDLL with 400fsrms integrated jitter, −55.6dBc reference spur and 20fs/mV supply-noise sensitivity using 1b TDC", 2012 IEEE International Solid- State Circuits Conference - (ISSCC), San Francisco, CA, IEEE, pp. 242 - 244, 02/2012.
Reddy, K., S. Rao, R. Inti, B. Young, A. Elshazly, M. Talegaonkar, and P K. Hanumolu, "A 16mW 78dB-SNDR 10MHz-BW CT-ΔΣ ADC using residue-cancelling VCO-based quantizer", 2012 IEEE International Solid- State Circuits Conference - (ISSCC), San Francisco, CA, IEEE, pp. 152 - 154, 02/2012.
Tong, T., W. Yu, P K. Hanumolu, and G. C. Temes, "Calibration technique for SAR analog-to-digital converters", 2012 IEEE International Symposium on Circuits and Systems - ISCAS 2012, Seoul, Korea (South), IEEE, pp. 2993 - 2996, 05/2012.
Weaver, S., B. Hershberg, P K. Hanumolu, and U. Moon, "A multiplexer-based digital passive linear counter (PLINCO)", Analog Integrated Circuits and Signal Processing, vol. 73, issue 1, pp. 143 - 149, 10/2012.
Sasidhar, N., D. Gubbins, P K. Hanumolu, and U. Moon, "Rail-to-Rail Input Pipelined ADC Incorporating Multistage Signal Mapping", IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 59, issue 9, pp. 558 - 562, 09/2012.
Tong, T., P K. Hanumolu, and G. C. Temes, "A semi-synchronous SAR ADC", Analog Integrated Circuits and Signal Processing, vol. 71, issue 3, pp. 407 - 410, 06/2012.
Hanumolu, P K., U. Moon, and T. S. Fiez, "Tutorial T5: Advanced Analog-Mixed Signal System and Circuit Techniques", 25th International Conference on VLSI Design, Hyderabad, India, IEEE, pp. 20 - 21, 01/2012.
2011
Elshazly, A., R. Inti, W. Yin, B. Young, and P K. Hanumolu, "A 0.4-to-3 GHz Digital PLL With PVT Insensitive Supply Noise Cancellation Using Deterministic Background Calibration", IEEE Journal of Solid-State Circuits, vol. 46, issue 12, pp. 2759 - 2771, 12/2011.
Elshazly, A., R. Inti, W. Yin, B. Young, and P K. Hanumolu, "A 0.4-to-3GHz digital PLL with supply-noise cancellation using deterministic background calibration", 2011 IEEE International Solid- State Circuits Conference - (ISSCC), San Francisco, CA, IEEE, pp. 92 - 94, 02/2011.
Inti, R., W. Yin, A. Elshazly, N. Sasidhar, and P K. Hanumolu, "A 0.5-to-2.5 Gb/s Reference-Less Half-Rate Digital CDR With Unlimited Frequency Acquisition Range and Improved Input Duty-Cycle Error Tolerance", IEEE Journal of Solid-State Circuits, vol. 46, issue 12, pp. 3150 - 3162, 12/2011.
Inti, R., W. Yin, A. Elshazly, N. Sasidhar, and P K. Hanumolu, "A 0.5-to-2.5Gb/s reference-less half-rate digital CDR with unlimited frequency acquisition range and improved input duty-cycle error tolerance", 2011 IEEE International Solid-State Circuits Conference - (ISSCC), San Francisco, CA, IEEE, pp. 438 - 450, 02/2011.
Yin, W., R. Inti, A. Elshazly, B. Young, and P K. Hanumolu, "A 0.7-to-3.5 GHz 0.6-to-2.8 mW Highly Digital Phase-Locked Loop With Bandwidth Tracking", IEEE Journal of Solid-State Circuits, vol. 46, issue 8, pp. 1870 - 1880, 08/2011.
Rao, S., Q. Khan, S. Bang, D. Swank, A. Rao, W. McIntyre, and P K. Hanumolu, "A 1.2A buck-boost LED driver with 13% efficiency improvement using error-averaged SenseFET-based current sensing", 2011 IEEE International Solid- State Circuits Conference - (ISSCC), San Francisco, CA, IEEE, pp. 238 - 240, 02/2011.
Rao, S., Q. Khan, S. Bang, D. Swank, A. Rao, W. McIntyre, and P K. Hanumolu, "A 1.2-A Buck-Boost LED Driver With On-Chip Error Averaged SenseFET-Based Current Sensing Technique", IEEE Journal of Solid-State Circuits, vol. 46, issue 12, pp. 2772 - 2783, 12/2011.
Khan, Q., S. Rao, D. Swank, A. Rao, W. McIntyre, S. Bang, and P K. Hanumolu, "A 3.3V 500mA digital Buck-Boost converter with 92% peak efficiency using constant ON/OFF time delta-sigma fractional-N control", ESSCIRC 2011 - 37th European Solid State Circuits Conference, Helsinki, Finland, IEEE, pp. 439 - 442, 09/2011.
Rao, S., B. Young, A. Elshazly, W. Yin, N. Sasidhar, and P K. Hanumolu, "A 71dB SFDR open loop VCO-based ADC using 2-level PWM modulation", 2011 Symposium on VLSI Circuits (VLSIC), pp. 270 -271, 06/2011.
Asl, S Z., S. Saxena, P K. Hanumolu, K. Mayaram, and T. S. Fiez, "A 77dB SNDR, 4MHz MASH ΔΣ modulator with a second-stage multi-rate VCO-based quantizer", 2011 IEEE Custom Integrated Circuits Conference (CICC), San Jose, CA, IEEE, pp. 1 - 4, 09/2011.
Agrawal, A., P K. Hanumolu, and G-Y. Wei, "Area efficient phase calibration of a 1.6 GHz multiphase DLL", 2011 IEEE Custom Integrated Circuits Conference (CICC), San Jose, CA, IEEE, pp. 1 - 4, 09/2011.
Wang, Y., P K. Hanumolu, and G. C. Temes, "Design Techniques for Wideband Discrete-Time Delta-Sigma ADCs With Extra Loop Delay", IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 58, issue 7, pp. 1518 - 1530, 07/2011.
Vytyaz, I., P K. Hanumolu, U. Moon, and K. Mayaram, "Design-Oriented Analysis of Circuits With Equality Constraints", IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 58, issue 5, pp. 1089 - 1098, 05/2011.
Talegaonkar, M., R. Inti, and P K. Hanumolu, "Digital clock and data recovery circuit design: Challenges and tradeoffs", 2011 IEEE Custom Integrated Circuits Conference (CICC), San Jose, CA, IEEE, pp. 1 - 8, 09/2011.
Lee, S., J. Chae, M. Aniya, S. Takeuchi, K. Hamashita, P K. Hanumolu, and G. C. Temes, "A double-sampled low-distortion cascade ΔΣ modulator with an adder/integrator for WLAN application", 2011 IEEE Custom Integrated Circuits Conference (CICC), San Jose, CA, IEEE, pp. 1 - 4, 09/2011.

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