OREGON STATE UNIVERSITY

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Biblio

Found 9 results
Filters: Keyword is low power  [Clear All Filters]
2012
Donkoh, E., and P. Y. Chiang, "A low-leakage dynamic register file with unclocked wordline and sub-segmentation for improved bitline scalability", Proceedings of the 2012 ACM/IEEE international symposium on Low power electronics and design, Redondo Beach, CA, ACM, pp. 155–160, 08/2012.
Crop, J., R. Pawlowski, and P. Y. Chiang, "Regaining throughput using completion detection for error-resilient, near-threshold logic", Proceedings of the 49th Annual Design Automation Conference - DAC '12, San Francisco, CA, ACM Press, pp. 974-979, 06/2012.
Donkoh, E., T S. Ong, Y N. Too, and P. Y. Chiang, "Register file write data gating techniques and break-even analysis model", Proceedings of the 2012 ACM/IEEE international symposium on Low power electronics and design, Redondo Beach, CA, ACM, pp. 149–154, 08/2012.
2011
Weaver, S. T., B. P. Hershberg, N. Maghari, and U. Moon, "Domino-Logic-Based ADC for Digital Synthesis", IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 58, issue 11, pp. 744 - 747, 11/2011.
2010
Ayers, J., K. Mayaram, and T. S. Fiez, "An Ultralow-Power Receiver for Wireless Sensor Networks", IEEE Journal of Solid-State Circuits, vol. 45, issue 9, pp. 1759 - 1769, 09/2010.
2005
Li, J., G-C. Ahn, D-Y. Chang, and U. Moon, "A 0.9-V 12-mW 5-MSPS algorithmic ADC with 77-dB SFDR", IEEE Journal of Solid-State Circuits, vol. 40, issue 4, pp. 960 - 969, 04/2005.
2004
Li, J., and U. Moon, "A 1.8-V 67-mW 10-Bit 100-MS/S Pipelined ADC Using Time-Shifted CDS Technique", IEEE Journal of Solid-State Circuits, vol. 39, issue 9, pp. 1468 - 1476, 09/2004.