OREGON STATE UNIVERSITY

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Biblio

Found 7 results
Filters: Author is Eshraghi, Aria  [Clear All Filters]
2004
Eshraghi, A., and T. S. Fiez, "A Comparative Analysis of Parallel Delta–Sigma ADC Architectures", IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 51, issue 3, pp. 450 - 458, 03/2004.
2003
Eshraghi, A., and T. S. Fiez, "A time-interleaved parallel ΔΣ A/D converter", IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, vol. 50, issue 3, pp. 118 - 129, 03/2003.
2002
Batten, R. D., A. Eshraghi, and T. S. Fiez, "Calibration of parallel ΔΣ ADCs", IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, vol. 49, issue 6, pp. 390 - 399, 06/2002.
Chilakapati, U., T. S. Fiez, and A. Eshraghi, "A CMOS transconductor with 80-dB SFDR up to 10 MHz", IEEE Journal of Solid-State Circuits, vol. 37, issue 3, pp. 365 - 370, 03/2002.
2001
Chilakapati, U., T. S. Fiez, and A. Eshraghi, "A 3.3 V transconductor in 0.35 μm CMOS with 80 dB SFDR up to 10 MHz", IEEE 2001 Custom Integrated Circuits Conference, San Diego, CA, IEEE, pp. 459 - 462, 05/2001.
2000
Radke, R. E., A. Eshraghi, and T. S. Fiez, "A 14-bit current-mode ΔΣ DAC based upon rotated data weighted averaging", IEEE Journal of Solid-State Circuits, vol. 35, issue 8, pp. 1074 - 1084, 08/2000.
1999
Radke, R., A. Eshraghi, and T. S. Fiez, "A spurious-free delta-sigma DAC using rotated data weighted averaging", IEEE 1999 Custom Integrated Circuits Conference, San Diego, CA, IEEE, pp. 125 - 128, 05/1999.