OREGON STATE UNIVERSITY

You are here

Colloquium Series

Once every week while school is in session, EECS invites a distinguished researcher or practitioner in a computer science or electrical and computer engineering-related field to present their ideas and/or work. Talks are generally targeted to electrical engineering and computer science graduate students. This colloquium series is free and open to everyone.

Upcoming Colloquia

Unsolved Problems in Acoustic Noise Cancellation

Monday, October 3, 2016 -
4:00pm to 4:50pm
DEAR 118

Speaker Information

Robert Adams

Abstract

In the past 20 years there has been an explosion in the application of acoustic noise cancellation (ANC) to combat environmental noise. ANC is now found in a wide range of consumer products ranging from headphones to automobiles. This talk will cover the basics of ANC, with examples from several industries, and discuss some of the fundamental limitations which presently limit the achievable performance.

Speaker Bio

Bob Adams graduated from Tufts University in 1976, and after spending several years as a musician, he began a career in the consumer/professional audio equipment market. In the late 1970’s he published the first paper on log-domain filtering, and then began working extensively in the brand-new area of sigma-delta A/D converters, producing the first audio converter with more than 16-bit resolution. In 1989 Bob joined the Analog Devices converter group, and worked on ADI’s early sigma-delta converter products. In the last 25 years he has pioneered many important architectural advances in sigma-delta converters including mismatch-shaping, multi-bit quantization, and continuous-time architectures. Bob also has a passion for digital signal processing, and produced the first integrated asynchronous sample-rate converter chip. After getting a taste of digital design, Bob founded the sigmaDSP line of audio-specific DSP cores. Bob has 38 patents (32 with ADI) , and is a Fellow of the IEEE, Fellow of the Audio Engineering Society as well as a Fellow of ADI. He received the Pederson award in Solid-State Circuits in 2015 and the Industrial Pioneer award from the Circuits-and-Systems society in 2016. He has published and taught extensively in his areas of expertise.

28-56Gb/s Standards and Design Implications

Monday, October 17, 2016 -
4:00pm to 4:50pm
DEAR 118

Speaker Information

Frank Omahony

Abstract

Over the past decade, wireline data rates have doubled about every four years to keep pace with aggregate system bandwidth requirements. Electrical signaling standards for networking, telecom and storage applications – including Ethernet and OIF-CEI – tend to be the first to define the path to increase line rates. Today, links up to 28Gb/s/lane are being widely deployed. Meanwhile, standards for 50-56Gb/s are being defined, and we are seeing early demonstrations of transceivers and components meeting this bandwidth. This presentation will provide an overview of standards, circuit architectures and design tradeoffs for 28-56Gb/s links. It will start by providing a summary of recent data rate scaling trends and standards for 28-56Gb/s and show where wireline is used in high-performance systems. Next it will describe the key tradeoffs for increasing aggregate bandwidth, including power, channel quality and process technology capability. Then it will discuss how recent standards have balanced these tradeoffs, and describe the implications for circuit architecture and design, including equalization, clocking, modulation and error correction. Finally we will summarize the existing design data points from industry and academic publications for 28-56Gb/s

Speaker Bio

Frank leads the I/O Circuit Technology group within Advanced Design at Intel in Hillsboro, Oregon, where he is a Principal Engineer. His group develops the first wireline I/O circuits for each new CMOS process technology. From 2003 until 2011 he was a member of the Signaling Research group in Intel’s Circuit Research Lab where his work focused on high-speed and low-power transceivers, clocking and on-die measurement techniques. Prior to joining Intel, Frank received the BS, MS, and PhD degrees in electrical engineering from Stanford University. Frank is the chair of the ISSCC Wireline Subcommittee and previously served as an Associate Editor for TCAS-I. He is a past recipient of the ISSCC Jack Kilby Award and TCAS Darlington Best Paper Award and is an IEEE Distinguished Lecturer.

The Quest for The Ultimate Learning Machine

Monday, October 24, 2016 -
4:00pm to 4:50pm
DEAR 118

Speaker Information

Pradeep Dubrey

Abstract

Traditionally, there has been a division of labor between computers and humans where all forms of number crunching and bit manipulations are left to computers; whereas, intelligent decision-making is left to us humans.  We are now at the cusp of a major transformation that can disrupt this balance. There are two triggers for this: first, trillions of connected devices (the “Internet of Things”) converting the large untapped analog world around us to a digital world, and second, (thanks to Moore’s Law) beyond-exaflop levels of compute, making a large class of structure learning and decision-making problems now computationally tractable. In this talk, I plan to discuss real challenges and amazing opportunities ahead of us for enabling a new class of applications and services, “Machine Intelligence Led Services”.  These services are distinguished by machines being in the ‘lead’ for tasks that were traditionally human-led, simply because computer-led implementations are about to reach and even surpass the quality metrics of current human-led offerings.

Speaker Bio

Pradeep Dubey is an Intel Fellow and Director of Parallel Computing Lab (PCL), part of Intel Labs. His research focus is computer architectures to efficiently handle new compute-intensive application paradigms for the future computing environment. Dubey previously worked at IBM's T.J. Watson Research Center, and Broadcom Corporation. He has made contributions to the design, architecture, and application-performance of various microprocessors, including IBM® Power PC*, Intel® i386TM, i486TM, Pentium® Xeon®, and the Xeon Phi™ line of processors. He holds over 36 patents, has published over 100 technical papers, won the Intel Achievement Award in 2012 for Breakthrough Parallel Computing Research, and was honored with Outstanding Electrical and Computer Engineer Award from Purdue University in 2014. Dr. Dubey received a PhD in electrical engineering from Purdue University. He is a Fellow of IEEE.

Past Colloquia

Jonathan Hurst
Monday, April 1, 2013 -
4:00pm to 4:50pm
Dr. Michael Dinitz
Thursday, March 14, 2013 -
8:30am to 9:45am
Amir Nayyeri
Monday, March 11, 2013 -
10:00am to 11:15am
Erin Chambers
Friday, March 8, 2013 -
10:00am to 11:15am
Philip J. Guo
Wednesday, March 6, 2013 -
10:00am to 11:15am
Matthew Taylor
Monday, March 4, 2013 -
4:00pm to 4:50pm
Mi Zhang
Thursday, February 28, 2013 -
8:45am to 9:45am
Charalampos Papamanthou
Wednesday, February 27, 2013 -
10:00am to 11:15am
Quanyan Zhu
Monday, February 25, 2013 -
10:00am to 11:00am

Pages