OREGON STATE UNIVERSITY

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Emerging Device Nanotechnology for Future Nanoelectronics Applications

KEC 1001
Monday, June 4, 2012 - 4:00pm to 4:50pm
Speaker Information
Robert Chau
Intel Senior Fellow
Technology and Manufacturing Group

This presentation will cover three topics. First, it will highlight some of the most recent device nanotechnologies implemented by the silicon industry for advanced CMOS transistors. Second, it will summarize research progress on non-silicon transistor channel materials (e.g. III-V, Ge) and their integration on silicon for future high speed and low power CMOS applications. Third, it will describe recent research effort by the device research community on forward-looking devices beyond CMOS. In this research space, carbon-based, spin-based, tunnel-based and exciton-based devices are being explored as alternative switches/devices to either replace or complement CMOS to improve and create new circuit functionalities for future nanoelectronics applications. These emerging devices exhibit unique and interesting characteristics which will be discussed.

 

Speaker Bio


Robert S. Chau is an Intel Senior Fellow and director of transistor research and nanotechnology in Intel's Technology and Manufacturing Group. Chau is responsible for directing research and development in advanced transistors and gate dielectrics, process modules and technologies, and silicon integrated processes for microprocessor applications. He is also responsible for leading research efforts in emerging nanotechnology for future nanoelectronics applications. Chau joined Intel in 1989, became an Intel Fellow in 2000 and an Intel Senior Fellow in 2005. During his career at Intel he developed nine generations of Intel gate dielectrics, including the high-K/metal-gate, along with many transistor innovations and process technologies used in various Intel manufacturing processes and microprocessor products. He also introduced many new process modules and novel device nanotechnologies for Intel's future logic processes. Chau has earned 7 Intel Achievement Awards. He was the co-recipient of the 2008 SEMI Award for North America for the development of Intel's 90nm strained silicon technology, and the 2008 EDN (Electronics Design, Strategy, News) "Innovator of the Year" award for the development of Intel's 45nm high-k metal gate transistor technology. Chau received his bachelor's and master's degrees and Ph.D. in electrical engineering from The Ohio State University. He holds more than 180 issued U.S. patents and has been elected an IEEE Fellow.