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Digital To Time Conversion (DTC) Based Direct Digital Frequency Synthesis: Spur analysis and mitigation

Monday, February 25, 2013 -
4:00pm to 4:50pm
KEC 1001

Speaker Information

Sumit A. Talwalkar
Phd Candidate
School of EECS
Oregon State University


<p>Frequency synthesizers are critical components of all communication systems. <span data-scayt_word="Wideband" data-scaytid="31">Wideband</span> (multi-octave), low settling time synthesizers are key <span data-scayt_word="enablers" data-scaytid="32">enablers</span> of a software defined radio (<span data-scayt_word="SDR" data-scaytid="33">SDR</span>). Digital-to-time conversion (<span data-scayt_word="DTC" data-scaytid="34">DTC</span>) is a relatively new type of direct digital synthesis (DDS). <span data-scayt_word="DTC" data-scaytid="35">DTC</span> has some promising unique advantages such as wide frequency range, fast switching between frequencies, lower power than traditional DDS and scalable <span data-scayt_word="integrability" data-scaytid="38">integrability</span> on <span data-scayt_word="CMOS" data-scaytid="39">CMOS</span>. One of the important challenges with the <span data-scayt_word="DTC" data-scaytid="36">DTC</span> architecture is the presence of spurs. This presentation considers the study of spurs and a method of spur mitigation. There are two important spur mechanisms: phase <span data-scayt_word="quantization" data-scaytid="40">quantization</span> and delay mismatches. Similar to traditional DDS, the <span data-scayt_word="DTC" data-scaytid="37">DTC</span> spur patterns are highly dependent on the choice of output frequency. We have developed a classification of output frequencies that allows a way to efficiently study spur patterns for <i>all</i> output frequencies using a close approximation. Controlled dithering is a method of generating effective fractional delay. It has been shown to be an effective method of spur mitigation in a 90 nm <span data-scayt_word="CMOS" data-scaytid="41">CMOS</span> implementation. Measurements also illustrate the trade-off between spurs and the noise floor. Finally a comparative analysis of the state of the art of integrated fast wide-band synthesizers will be presented that shows <span data-scayt_word="DTC" data-scaytid="42">DTC</span> to be a compelling candidate.</p>

Speaker Bio

Sumit A. Talwalkar is a PhD candidate at EECS. He is a Principal IC Systems Engineer with Motorola Solutions, Inc., in Plantation, FL. He got B.Tech in EE from the Indian Institute of Technology, Mumbai, India in 1992 and MS in EE from the University of Rhode Island in Kingston, RI in 1995. He is currently working towards his Ph.D. in ECE at Oregon State University in Corvallis, OR on the topic of modeling and analysis of digital to time conversion (DTC) direct digital synthesizers. His interests include signal processing, communications and IC systems modeling and analysis.