Monday, May 5, 2014 - 4:00pm to 4:50pm
KEC 1001

Speaker Information

Nader Bagherzadeh
Professor
Department oF EECS
University of California, Irvine

Abstract

In this talk the notion of 3D NoC will be presented. The combination of 3D integration and NoC technologies is considered the promising candidate for the next generation high-performance and low-power on-chip interconnect design. In particular, the idea of utilizing TSVs for communication among different layers of 3D NoC is discussed. TSVs support higher bandwidth, smaller form factor, shorter wire length, lower power, and better performance than simple wires. They are currently known as the most popular communication mechanism among planar surfaces of a 3D chip, but they introduce signal integrity problems that can impact correct operation of the device. This talk will give an overview of some of the reliability issues for 3D NoCs and discuss new ideas for handling those problems.

Speaker Bio

Nader Bagherzadeh is a professor of computer engineering in the department of electrical engineering and computer science at the University of California, Irvine, where he served as a chair from 1998 to 2003. Dr Bagherzadeh has been involved in research and development in the areas of: computer architecture, reconfigurable computing, VLSI chip design, network-on-chip, 3D chips, sensor networks, and computer graphics since he received a Ph.D. degree from the University of Texas at Austin in 1987.

Professor Bagherzadeh has published more than 200 articles in peer-reviewed journals and conferences. He has trained hundreds of students who have assumed key positions in software and computer systems design companies in the past twenty years. He has been a PI or Co-PI on more than $8 million worth of research grants for developing next generation computer systems for applications in general purpose co mputing and digital signal processing.