Thursday, April 2, 2015 - 8:45am to 9:45am
KEC 1007

Speaker Information

Tejasvi Anand
PhD Candidate
University of Illinois, Urbana-Champaign


Intra- and inter-chip communication links in both high performance compute systems and mobile platforms consume significant fraction of the system power. Technology scaling combined with techniques such as near-threshold operation and dynamic voltage and frequency scaling have greatly improved energy efficiency of computation kernels. As a result, the fraction of power consumed by communication links is bound to increase steadily. In view of this, there have been many efforts to aggressively improve the energy efficiency of links. Such efforts have mainly focused on improving energy efficiency at the link building blocks operating at peak performance. Unfortunately these improvements do not necessarily translate to energy savings at the system level because links are seldom fully utilized at peak performance. In other words, energy efficiency degrades drastically in many practical applications where links are only sporadically utilized. In this talk, I will present circuit- and system-level techniques to achieve excellent energy efficiency across a wide range of link utilization levels, thereby achieving energy proportional behavior (energy consumed is proportional to amount of data transferred). To this end, I will illustrate that by operating links with rapid power state transitions, significant power savings can be achieved. Key design challenges and techniques to overcome practical limitations of rapid power state transition in serial links will be discussed. Experimental results to prove the effectiveness of proposed techniques will be presented. Future application of these techniques could include achieving energy proportionality in other communication channels.

Speaker Bio

Tejasvi Anand is a PhD Candidate at UIUC working on wireline and sensor systems. He received his M.Tech. degree (with Distinction) in electronics design and technology from the Indian Institute of Science, Bangalore, India, in 2008. From 2008 to 2010, he worked as an Analog Design Engineer at Cosmic Circuits (now Cadence), Bangalore, India. At Cosmic Circuits he was involved in designing pipeline analog to digital converters, for wireless receivers. From 2010 to 2011, he worked as a Project Associate at the Indian Institute of Science, Bangalore where he was involved in designing SAR analog to digital converters for neural recording systems. Tejasvi is a recipient of IEEE Solid State Circuit Society Pre-Doctoral Achievement Award, M. E. Van Valkenburg Graduate Research Award from the University of Illinois, Analog Devices Outstanding Student Designer Award, and CEDT Design (Gold) Medal from the Indian Institute of Science, Bangalore.