TekBots

Class,
The final lab for ECE 272 has a few updates:
1. C1 on the ADC board is backwards and needs to be flipped. It's a surface mount part, but it's a bigger one. It shouldn't be too hard remove and flip.

2. The final project is divided into three phases on the white board in Dearborn 203. Displaying multi-digit numbers from the button board onto the 7 segment display is phase 1. Displaying ADC values onto the display is phase 2, and connecting the ADC to a test pad on the TekBot is the final stage.

3. A chunk of Verilog is posted on the 272 website that will help you use the ADC.


Good luck, and make sure to leave course comments about ECE 272 at the end of the term. We will use these to improve the course for future students.

From a 272 Student,

Dividing by 10 in my verilog code produces correct outputs in simulation, but not on my FPGA. Dividing by 2 then by 5 works as expected. So does dividing by 11. I initially encountered this problem while debugging my section 6 code (which is fully functional with the divide by 2 then 5 trick), but the following module is sufficient to reproduce the bug on my machine.

module top(
input [7:0]in,
output reg [7:0]out
);

always @ (*)
out = ~(in / 10);

endmodule


reply from Matt Shuman:
http://stackoverflow.com/questions/1172 ... in-verilog


Progress from student:

I discovered that " / 10" synthesizes correctly when Synplify Pro is used for synthesis. It also works correctly with Lattice LSE if you use a signed type, such as reg signed [8:0]. That is why using the integer type (which I believe is an alias for reg signed [31:0] ) solved the problem (one of the TAs suggested this solution to me). Although it seems from the SO thread that division often cannot be synthesized, if it's going to be needed for the 272 lab it would be nice to include one of the above solutions in the manual. I don't know if other people even had this problem. I may be using a different version of Diamond (I have 3.1.0.96).