This presentation will review concepts in duty-cycle based resistance tuning and how these concepts can be used to create low-voltage, highly-linear, tunable circuits. Besides looking at continuous time filters we will also explore bandwidth tunable mixers and delta-sigma modulators. The continuous downscaling of transistor dimensions in CMOS technology has enabled digital IC systems to achieve increasingly higher speed and integration density. An important aspect of this downscaling trend is that supply voltages must be decreased along with transistor dimensions. While digital circuits benefit from supply voltage scaling with lower power dissipation, the design of low-voltage analog circuits that must co-exist with digital circuits poses many difficult challenges. Integrated continuous-time (CT) filters and ΔΣ ADCs are particularly sensitive to low supply voltages. One of the most critical issues in these types of circuits is resistance and capacitance variation caused by changes in process, voltage and temperature (PVT). PVT variations in CT integrated filtering circuits can cause corner frequency variation by up to 50%. To suppress this time-constant variation, voltage controlled tunable elements such as MOS resistors or MOS capacitors are often used. Problems occur when the supply voltage is lowered, because the tuning range of the voltage-controlled elements is lowered as well. A low supply voltage causes the resistance to become highly sensitive to variations in the control voltage and supply voltage. If the supply voltage is low enough, the available tuning range may not be enough to compensate for PVT variations. Duty-cycle based tuning has been shown to provide a large tuning and high linearity at low supply voltages. Because tuning is done in the time domain rather than the voltage domain, the tuning range is independent of the supply voltage.

Biography

Peter Kurahashi received the B.S. degree in electrical engineering from Oregon State University, Corvallis, in 2004. During the summer of 2002 he worked at Planar Systems Inc., Beaverton, OR, researching display technologies. During the summer of 2003 he worked at Hewlett Packard, Corvallis, OR, helping develop molecular memory devices. He is presently working toward the Ph.D. degree in electrical engineering and computer science at Oregon State University. His research interests include filters, mixers, data converters and low-voltage circuit design. He received the Custom Integrated Circuits Conference (CICC) Best Student Paper Award in 2006 and the Analog Devices Outstanding Student Designer Award in 2007.