A Wideband Low-Power Continuous-Time Delta-Sigma ADC
Delta-sigma ADCs are key building blocks in wireless communication systems due to their high dynamic range and excellent power efficiency. With increasing signal bandwidth requirements, the continuous-time delta-sigma ADC has become popular because it can achieve higher bandwidth or lower power dissipation compared to its discrete-time version.

In this thesis proposal, a new continuous-time cascaded delta-sigma ADC is presented, which can achieve 12 bit resolution within a 20 MHz signal bandwidth. The MASH 2-2 architecture is used for its good stability and high interstage gain. The low-distortion technique, which has been effectively used in discrete-time ΔΣ modulators, has been modified to reduce the excess-loop delay effect, and thus made applicable in continuous-time structures. A front-end passive low-pass filter is used to eliminate out-of band peaking, which is a common issue in continuous-time ΔΣ ADCs with feed-forward architecture. Finally, a digital compensation filter is designed to adaptively correct the quantization noise leakage due to the analog circuit noidealities. With a 90-nm CMOS technology, simulations indicate that the proposed ADC can achieve a 12 bit resolution with a 20 MHz signal bandwidth and a power dissipation around 25mW.