Metal Fill Considerations for On-Chip Interconnects and Spiral Inductors
Variability in circuit performance due to process defects is a major concern in integrated circuit (IC) fabrication. Advanced IC manufacturing processes employ Chemical-Mechanical Polishing (CMP) for planarization of oxide and metal layers. CMP defects result in variations in the oxide and metal topographical profile. To reduce these topographical variations, electrically non-functional (dummy) metal features are added in low metal density regions. These metal fills degrade the performance of on-chip interconnects and components, and the overall circuit due to the additional electrical parasitics. Therefore, it is important to characterize the parasitic effects of metal fill on critical structures such as interconnects and spiral inductors.

This thesis presents a study of the impact of metal fill placement, size, and shape on the electrical performance of representative on-chip transmission line structures and spiral inductors. We separate the electric and magnetic effects of different metal fill designs by studying their impact on parasitic capacitance and eddy-current loss. The study is done through simulation using a commercial full-wave electromagnetic simulator and measurement of a test chip fabricated in a 180nm BiCMOS process, and is supported through theoretical considerations. For a reduction in fill size of about 90% while keeping the same metal density, we find a significant reduction in parasitic microstrip capacitance and microstrip resistance by about 30% compared to the larger fill size. Similarly, a 70% decrease in fill size provides an improvement of about 13% in measured quality factor of a representative spiral inductor design. Using octagonal metal fill shapes reduces the parasitic microstrip capacitance by about 45% and microstrip resistance by about 13% compared to square shapes with the same metal density. Furthermore, measurement results for a spiral inductor show larger impact on the quality factor and self-resonance frequency for off-plane metal fill compared to in-plane metal fill.

Low Power Design Techniques for Analog-to-Digital Converters in Submicron CMOS
Advances in process technologies have led to the development of low-power high speed digital signal processing blocks that occupy small areas. However, the design of analog building blocks, especially analog-to-digital converters (ADCs), becomes complex and power-inefficient with each advance in process node due to decreasing swing and intrinsic gain. This work introduces circuit techniques that enable the design of low-complexity power-efficient ADCs in submicron CMOS. The techniques include replacing the power-hungry opamp in integrators, used in delta-sigma modulators, with low power zero-crossing-based ones. Also proposed is an enhanced correlated level shifting technique that allows the use of simple low gain opamps to realize high performance pipelined ADCs. Fabricated prototypes of the delta-sigma and pipelined ADCs, along with their simulation and measurement results, are employed to discuss the effectiveness of the techniques in achieving compact low-power designs.