A Wideband Low-Power Continuous-Time Delta-Sigma ADC
Delta-sigma ADCs are key building blocks in wireless communication systems due to their high dynamic range and excellent power efficiency. With increasing signal bandwidth requirements, the continuous-time delta-sigma ADC has become popular because it can achieve higher bandwidth or lower power dissipation compared to its discrete-time version.

In this thesis proposal, a new continuous-time cascaded delta-sigma ADC is presented, which can achieve 12 bit resolution within a 20 MHz signal bandwidth. The MASH 2-2 architecture is used for its good stability and high interstage gain. The low-distortion technique, which has been effectively used in discrete-time ΔΣ modulators, has been modified to reduce the excess-loop delay effect, and thus made applicable in continuous-time structures. A front-end passive low-pass filter is used to eliminate out-of band peaking, which is a common issue in continuous-time ΔΣ ADCs with feed-forward architecture. Finally, a digital compensation filter is designed to adaptively correct the quantization noise leakage due to the analog circuit noidealities. With a 90-nm CMOS technology, simulations indicate that the proposed ADC can achieve a 12 bit resolution with a 20 MHz signal bandwidth and a power dissipation around 25mW.

Learning MDP Action Models via Discrete Mixture Trees
This thesis addresses the problem of learning dynamic Bayesian network (DBN) models to support reinforcement learning. It focuses on learning regression tree models of the conditional probability distributions of the DBNs. Existing algorithms presume that the stochasticity in the domain can be modeled as a deterministic function with additive noise. This is inappropriate for many RL domains, where the stochasticity takes the form of a random choice over deterministic functions. This paper introduces a regression tree algorithm in which each leaf node is modeled as a finite mixture of deterministic functions. This mixture is approximated via a greedy set cover. To combat overfitting, pruning techniques incorporating log likelihood and KL-Divergence are employed. Experiments on three challenging RL domains, two with stochastic variants, show that this approach finds trees that are more accurate and that are more likely to correctly identify the conditional dependencies in the DBNs based on small samples.

Low-Power Double-Sampled Delta-Sigma ADC for Broadband Applications
High speed and high resolution Analog-to-Digital Converter is a key building block for wide-band wireless communications, high definition video applications and medical images. By leveraging the down scaling of the latest CMOS technology and the noise shaping properties, Delta-Sigma ADCs are able to achieve wide-band operation and high accuracy simultaneously. The design of a switched capacitor 12-bit Delta-Sigma ADC with a 20MHz signal bandwidth is presented here.

To achieve very low power consumption, this ADC utilizes the following three design techniques:

1. Double sampling to increase the effective over-sampling ratio.
2. Capacitor reset technique allows the use of only one feedback DAC to fully eliminate the quantization noise folding back.
3. High gain wide bandwidth two-stage opamps are designed to minimize the quantization noise leakage.

A 2+2 cascaded topology with 3-bit internal quantizer is used in this Delta-Sigma ADC to adequately suppress the quantization noise while guarantee the loop stability. This ADC is designed and will be fabricated soon in 90nm pure digital CMOS process. Simulated power consumption is less than 20mW with a power supply of 1.2V.

Substrate Noise Coupling in Ring VCO-Based Phase Locked Loops
In this thesis, the performance degradation of a phase-locked loop due to substrate noise is examined. A new analytical equivalent circuit model for substrate noise coupling is derived for a heavily doped silicon substrate. The model has been validated with measured data from a 0.35 μm CMOS process. Since the model is physical, it can be used to predict substrate noise coupling without the need for extensive computer simulations using three-dimensional finite difference or Green's function solvers.

This is followed by an evaluation of the effect of substrate noise in a PLL. A PLL test chip fabricated in a 0.13 μm CMOS process has been characterized over a wide range of substrate noise frequencies. The measured results combined with extensive simulations provide insight into the mechanisms for noise coupling in a PLL. Based on an understanding of the noise coupling, guidelines for minimizing the impact of substrate noise are presented.

Fluid Flow on Interacting, Deformable Surfaces
Fluid simulation is an interesting research problem with a wide range of applications including mechanical engineering, special effects in movies and games, and scientific simulation. Due to the complex nature of typical fluid flow equations, there are circumstances where a full volumetric fluid simulation may not be necessary to generate the desired effect. Fluid flow on surfaces, such as in the case of rain-drops or moving rivers, can be solved more effectively by using a surface simplification to the normally expensive 3D Navier-Stokes equations. We present such a system in which the user can guide fluid flow on surfaces that are not only deforming, but also colliding with other surfaces in an environment. We also describe a technique for rendering the fluid on surfaces as a height field, which allows nearly volumetric effects to be achieved through a computationally less expensive surface simulation. Such a framework, we believe, can be extended to allow interactive control and visualization of surface flows carving into surfaces.

Power performance of multiplication on multi-cores using in Cryptosystem
The Advent of multi-core makes people have dreams which same job will be done at double or more performance. Cryptographers also think that cryptographic operation on the multi-cores are more efficient than single-cores, since the cryptosystem uses long-bit words for their own crypto-algorithm. By using parallelizing the long-bit words operation on multi-cores, the cryptosystem can achieve a performance improvement.

However all long-bit words using in the cryptosystem are not suitable for on multi-cores. Especially long-bit words, in elliptic curves cryptography (ECC), are not fit to the multi-cores system word size. Our experiment shows some idle cores by fixed word size. The idle cores are vulnerable to cryptosystem analysts or hackers. They can guess what fields are used in cryptosystem.

In a cryptosystem, multiplication is most important part particularly in the public key cryptosystem. Long-bit word multiplication operations are needed for encryption and decryption. J. Fan et al proposed using Montgomery multiplication on multi cores [25, 26]. Fan’s Montgomery fit with the computer system words like 16-bit or 32-bit. Fan uses GF(2256) for an example. Fan’s Montgomery is suitable for RSA, however in ECC, it could cause some idle core depending on what GF is used in the cryptosystem. If we use unbalanced field which is not fit for system words like GF(2131), we will get an idle cores and needless power consumption. And also, the last word is always less then system-word size, i.e., 32 bits or 16 bits.

In this thesis, we will present a word-size adjustment technique for last words to fit multi-cores. By adjustment of word-size, we can improve performance and power efficiency using idle cores on fixed word sizes. And it also shows that inserting random instruction, which can confuse cryptosystem analyst, increases efficiency on multi-cores even though it adds some workload.

Power Efficient H.264 Video Decoding in Embedded Multiprocessor
This paper presents a novel methodology that enables power efficient video decoding in an embedded system based on MPSoC (Multiprocessor System on Chip). This methodology is a hybrid of the parallel processing which reduces power consumption of processors by exploiting thread-level parallelism and the Dynamic Voltage Frequency Scaling (DVFS) capability that utilizes slack time for each frame with processor granularity. The video decoding process must be well optimized to improve performance continuously due to the many complex computation units. Since these intense computation functions have their own specific patterns, they were mainly performed by specialized hardware devices. This kind of device, one that combines a main processor and an Intellectual Property (IP), still dominates the multimedia market place because of its adjustable performance, power, and convenience of manufacturing, even though the multi-core embedded processor was released a few years ago. Our approach exploits inherent advantages of the multiprocessor without additional hardware implementation, and presents a thorough analysis of multiprocessor in an embedded system. An application we target is H.264/AVC, a well-adapted video coding standard for current multimedia environment which is used for many portable devices. We improve performance and power reduction by using a unified approach that combines parallel processing and DVFS.

Automated Analysis, Design, and Optimization of Low Noise Oscillators
Low noise oscillators are universally needed in digital systems for clock generation and synchronization, and in radio-frequency communication front-ends for frequency up- and down-conversion. Noise in oscillators results in timing jitter, and limits the clock frequency of digital systems. In radio-frequency communication systems, phase noise in oscillators lowers the signal-to-noise ratio of transmitters and receivers, and degrades the overall bit-error-rate. Therefore, accurate simulation and optimization of oscillator noise performance is of utmost importance.

The focus of this dissertation is on automated analysis, design and optimization of low noise oscillators. Several advances in oscillator analysis that facilitate automated oscillator design and optimization are presented. These include a new sensitivity analysis for oscillators, a design-oriented circuit analysis technique, and an oscillator design optimization approach. The sensitivity analysis calculates sensitivities of an oscillator's periodic steady-state and perturbation projection vector to design, process, or environmental parameters. In the design-oriented approach to circuit analysis the circuit response is computed together with the values of circuit parameters that result in a desired circuit performance. These analyses form the foundation for an efficient oscillator optimization technique that is general and applicable to all oscillator types.

Fast Handoff in WLAN and Behavior Based Mobility Prediction
Wireless Networks have been widely adopted into a major part of today's network infrastructure. They have become a popular technology to not only expand the coverage of wired networks but also to interconnect a large wireless networks, i.e., wireless mesh networks.

As they allow more flexible communication than traditional wired-networks some challenges are raised, such as maintaining a seamless connectivity when MSs move across the cells and dynamically adjusting resources for the transit MSs. Many solutions have proposed using mobility prediction to allow network devices and applications to prepare and adjust before the actual movement. However, none of the existing work considers mobility related to human factors.

Therefore, this thesis proposes a technique called Behavior-based Mobility Prediction (BMP) that captures the dynamic behavior of MSs and the network by considering location, group, time-of-day, and duration factors. The proposed BMP is targeted to provide accurate next-AP predictions for WLANs to minimize the handoff latency.

Moreover, the prediction can also apply to resource allocation in any type of Wireless Networks. Our simulation study shows that BMP virtually eliminates the need to scan for APs during handoffs and results in much better overall handoff delay compared to existing methods.

Digital Pulse Shape Discrimination Methods for Triple-Layer Phoswich Detectors Using Wavelets and Fuzzy Logic
A two-channel data acquisition system for simultaneous detection and discrimination of beta particles and gamma rays has been developed. Each channel measures and analyzes the input pulses which are the result of the absorption of radiation in the layers of the detector. The detector is a triple-layer phoswich (phosphor sandwich) scintillation detector followed by a photomultiplier tube (PMT). The PMT amplifies the photons and converts the photons to an electric signal. The signal is digitized and sent to the host computer for further processing. Two new digital algorithms based on Fuzzy Logic and on the Continuous Wavelet Transform have been developed and are discussed in this thesis.

In the first method, a de-noising algorithm based on the Wavelet Transform is implemented to reduce the effect of noise introduced by the noisy analog channel and by the photomultiplier tube. Three new timing features are extracted and given as input to a fuzzy interface system. The main goal of fuzziness in data set is to reduce the system complexity and to provide a model that allows for approximate results. Compared to the non-fuzzy method which was originally implemented for this detector, the fuzzy algorithm shows a better performance in separating beta and gamma spectra, especially at high energies. Also absorption in multiple layers is detected more efficiently.

The second algorithm is based on the Continuous Wavelet Transform. The novelty of this method consists in using scale-domain features. Since the output pulse shape of the photomultiplier tube is a non-stationary signal, conventional Fourier methods are not efficient for analyzing these signals and most of the existing pulse shape discrimination methods use time-domain features. Therefore, a time-frequency space is better suited to analyze these non-stationary signals. This method shows a better performance over existing time-domain methods in terms of robustness to noise and reliability.

The simultaneous detection of beta particles and gamma rays has several applications (for instance detection of underground nuclear explosions). The methods presented in this thesis could also be used in alpha/beta/neutron/gamma discrimination systems for cancer diagnosis and treatment.

1/f Noise Of GaAs Resistors On Semi-Insulating Substrates, And 1/f Noise Due To Temperature Fluctuations In Heat Conduction
This research work focuses on the mechanism of 1/f noise in GaAs resistors on semi-insulating substrates and 1/f noise due to temperature fluctuations in heat conduction in bipolar transistors. The goal of this research is to generate accurate models to explain physical origin of 1/f noise in semi-insulating substrate and semiconductor devices dissipating high power.

The model is based on a distributed equivalent circuit representation of the substrate, and shows that 1/f noise is a bulk phenomena associated with high resistivity substrates. One consequence of the theory is that in this particular instance Hooge's parameter is given by a formula.

Power dissipation at high currents and voltages in semiconductor devices results in significant heat generation and heat conduction towards the heat sink. The device temperature is only an average value and there are as a consequence of the diffusion equation for heat flow itself temperature fluctuations about this average value. It will be shown that these temperature fluctuations can result in 1/f noise at moderately low frequencies where these frequencies are determined by the physical dimensions over which the heat flows and the diffusion transit time. The results are then related to the shot noise or white noise due to the collector current allowing a determination of the 1/f noise corner frequency.

Thread Level Speculation for Multicore Systems
Thread Level Speculation (TLS) has been an intense research subject due to its ability to overcome the limitations of exploiting Instruction Level Parallelism (ILP) on high-performance, superscalar processors. One method of exploiting TLS is through Dynamic Speculative Multithreading (D-SpMT) that extracts multiple from a sequential program without compiler support or instruction extensions. The presentation will discuss the performance evaluation of a D-SpMT architecture called Cascadia, which uses an asymmetric multi-core architecture and provides multi-grained thread-level support in order to maximize TLP performance. Based on the results and knowledge gained through the validation of Cascadia, our future goals are to extract TLS automatically from the source code. This allows us to test a wider range of applications on existing technologies without the need for complex hardware implementations.

Automated MS Word Reformatting Tool for DAS
For disabled students, having accessible class materials is critical for their success in education. Disability Access Services at Oregon State University responds to the needs of these students and provides a service to reformat the materials to a suitable format for each student. One of these formats is a word document in a format that can be read by a text reader.

The purpose of this project is to automate the reformatting process for word documents that are used by the visually impaired students at Oregon State University. The automated process makes the reformatting process more efficient and less prone to human errors. The reformatting result also complies with the international accessible standards, DAISY and NIMAS.

Network Coding Techniques for Multimedia Transmissions
Multimedia streaming over lossy packet networks, such as wireless networks or the Internet, is challenging due to a number of factors, including high bit rates, delay sensitivity, loss sensitivity, and inter-dependency of media data. As such, there are many media streaming solutions ranging from source coding and channel coding to transport protocols. Recently, network coding has been introduced to efficiently utilize the throughput of multicast networks. This research investigates the application of network coding for multimedia streaming over wireless networks and the Internet. In particular, this research demonstrates that: (1) network coding can improve the multimedia multicast throughput, and (2) network coding can be integrated with a number of scheduling algorithms to maximize the multimedia quality. A number of simulations in some streaming scenarios will be presented to confirm the advantages of network coding.

Random Telegraph and 1/f Noise in Deep-submicron Metal-Oxide-Semiconductor Transistors
Random Telegraph noise has become a major concern now that MOS transistors in standard production are well below the 100nm node. Device performance in memories, analog circuits, and rf circuits are negatively impacted by the increasing RTS noise. We will describe the physical aspects of the noise and the effects RTS has on circuits. A few techniques have been proposed to reduce RTS noise in various circuit applications but many of these techniques are far short of being a complete solution. This research focuses on novel RTS noise analysis and remediation techniques not yet demonstrated. One proposed modification which is showing promise is to modify the doping in the active region. Further work remains on the doping dependence of the RTS noise which is just one aim of this research.

Gender HCI and Problem-Solving Strategies
Problem-solving software is meant to support both male and female users, but evidence is beginning to emerge that it does not. We suspect that the reported gender differences go deeper than mere features to the strategies themselves, and this is what we propose to investigate. Attending to strategies users would like to use when accomplishing a problem-solving task is foundational knowledge that is necessary for designing software features that genuinely support the users they are trying to reach. Yet, there has been no real attention to end users’ problem-solving strategies in the past, males’ or females’. This thesis proposes to help fill this critical gap by examining where strategies fit in the overall problem-solving process (using the sensemaking model), what underlying factors might affect strategy adoption (ex. epistemological style, self-efficacy, information processing style), and how these strategies can best be supported through problem-solving software features.

Development of a Barcode Integrated SQL Database Web Application in Tree Genetic Research Lab
Genetic engineering and genetic modification are techniques used to introduce new characteristics to an organism in order to increase its usefulness. The application of genetic engineering techniques to plants has produced beneficial consequences, such as an increase of Vitamin A level in rice, improvement of plant resistance to insects and herbicides, and alteration of plant chemistry to facilitate pulp production in the tree industry. Tree Biosafety and Genomics Research Cooperative (TBGRC) is a National Science Foundation Industry/University Research Center aiming at developing genetic technologies based on research in plant molecular biology that have potential applications to forest industries. Its research is presently focused on genetic engineering and functional genomic studies. Key research themes include genetic control of flowering, environmental analysis of transgenic plantations, and use of gene transfer for functional genomics. The core facility in TBGRC to carry out the research is the tissue culture laboratory, where the transgenic plants containing modified genes are produced. A barcode-integrated Web application was developed to facilitate the tissue culture processes in the laboratory. The whole system is comprised of three units: the barcode system, an SQL database, and a Web application implemented in C#/ASP.NET. The barcode system consists of BarFontTM barcode generating software, a barcode label printer from Zebra Technologies, and an IMAGETEAMTM 3800 hand held barcode scanner. The relational database data schema contains six tables and 39 data fields in which the unique barcode functions as an identity key for each tissue culture group. The barcode-integrated Web application consists of 11 major Web pages, with summarized function in the following table:

The barcode-integrated Web application greatly increases the efficiency of the tissue culture process. The application can, 1) provide a report of tissue culture experiments performed during a specific period to facilitate experiment planning and medium preparation at different steps in plant regeneration; 2) provide a history of an individual tissue culture group; 3) provide information on transgene origin (DNA construct, Agrobacterium strain) of transgenic plants involved in current experiments; 4) enable information to be conveniently and efficiently recorded in the lab by entering data via computer and retrieved by scanning bar code label; 5) quickly sort and summarize information regarding experiments in process based on criteria such as constructs, protocol, and projects, and generate various types of data reports. Eleven users in TBGRC have used the application and more than 1,100 transgenic plants have been generated using the application. Two new protocols for genetically transforming plants are under development using the application. The application reduces work burden and increases efficiency and accuracy of data recording and tracking. As a research program it significantly facilitates data analysis and evaluation. Overall the application has been proven to be an excellent assistant to the TBGRC tissue culture laboratory.

Low Power High-speed Pipelined ADCs
Real world is analog but the processing of signals can best be done in digital domain. So the need for Analog to Digital Converters (ADCs) is ever rising as more and more applications set in. With the advent of mobile technology, power in electronic components is being driven down to get more battery life. And because of their ubiquitous nature, ADCs are prime blocks in the signal chain which people have turned to to reduce power. In this research on Low Power High-speed Pipelined ADCs, two techniques to reduce power have been proposed. The first is the Capacitor and Opamp Sharing Technique and the second is the Hybrid architecture which makes use of asynchronous conversion concepts. The first technique has been implemented in Silicon and the measurement results which prove the technique will be presented. The second concept is in design stage and will be fabricated soon.

Effective Training and Feature Induction in Sequential Supervised Learning
Sequential supervised learning problems arise in many real applications. This thesis focuses on two important research directions in sequential supervised learning: feature induction and efficient training.

In the direction of feature induction, there will be two major contributions. First, I will further analyze the performance of the TreeCRF algorithm, a major CRF training algorithm that can induce nonlinear features in the training process. I will also study the problem of handling missing input values in CRFs, which has been rarely discussed in the literature. Two missing values methods specific to TreeCRF algorithm will be compared with two standard methods, and a guideline will be given as to which method is preferred in a given situation. Second, I will provide a new general method to induce nonlinear features for margin based classifiers instead of using the kernel trick. This will be done by optimizing unconstrained primal loss functions directly with functional gradient tree boosting. This method will be applied both to ordinary SVMs and to margin based structured classifiers, and it is expected to achieve comparable performance with faster training speed.

In the direction of efficient training, I will provide further understanding of two existing efficient learning frameworks: sequential error-correcting output coding and search based structured learning. I will discuss the limitations of these two frameworks and provide possible improvements for each.

Solving Multiagent Assignment Markov Decision Processes
Multiagent Assignment Markov Decision Processes are special cases of MDPs where several collaborative agents are assigned tasks by a centralized controller. I propose a method based on decomposing the action selection into an upper assignment level and a lower task performance level. The assignment problem is solved by search, while the lower task level is solved through reinforcement learning. In addition, I show how previous work on coordination graphs can be used for coordinating the agents at the lower level. I present empirical results in a large Multiagent predator-prey domain demonstrating that both assignment level search and task level coordination can together outperform either method alone.

High Efficiency Delta-Sigma Modulation Data Converters
Enabled by continued device scaling in CMOS technology, more and more functions that were previously realized in separate chips are getting integrated on a single chip nowadays. The mature integration on silicon has opened the door to new portable wireless applications, and initiated a widespread use of these devices in our common everyday life. Wide signal bandwidth, high linearity and dynamic range, and low power dissipation are required of embedded data converters that are the performance-limiting key building blocks of those systems. Thus, power-efficient and highly-linear data conversion over wide range of signal bands is essential to get the full benefits from device scaling. This continued trend keeps relentless innovation in the design of data converter continuing.

Traditionally, delta-sigma modulation data converters proved to be very effective in applications where high resolution was necessary in a relatively narrow signal band. There have been active research efforts across academia and industry on the extension of achievable signal bandwidth without compromising the performance of these data converters. In this dissertation, architectural innovations, combined with effective design techniques for delta-sigma modulation data converters, are presented to overcome the associated limitations. The effectiveness of the proposed approaches is demonstrated by experiments with the following state-of-the-art prototype designs: (1) a 0.8 V, 2.6 mW, 88 dB dual-channel audio delta-sigma modulation D/A converter with headphone driver; (2) an 8.1 mW, 82 dB self-coupled delta-sigma ADC with 1.9 MHz bandwidth and -97 dB THD; (3) an 88 dB ring-coupled delta-sigma ADC with 1.9 MHz bandwidth and -102.4 dB THD, (4) a multi-cell noise-coupled delta-sigma ADC with 1.9 MHz bandwidth, 88 dB DR, and -98 dB THD; (5) a noise-coupled time-interleaved delta-sigma ADC with 4.2 MHz bandwidth, -98 dB THD, and 79 dB SNDR; (6) a noise-coupled time-interleaved delta-sigma ADC with 2.5 MHz bandwidth, -104 dB THD, and 81 dB SNDR. As an extension of this research, two novel architectures for efficient double-sampling delta-sigma ADC and improved low-distortion delta-sigma ADC are proposed, and validated by extensive simulations.

A Survey of Continuous-Time ΔΣ Modulators
Recently, delta-sigma modulation has become a widely applied technique for high-performance analog-to-digital conversion of narrow-band signals. Most of the early designs used discrete-time structure for good accuracy and good linearity. The transfer functions are independent of the clock frequency. However, high unity-gain bandwidths of the opamps are required to satisfy the settling accuracy required in the discrete-time designs. Continuous-time structure can potentially achieve higher clock frequency with less power consumption. the anti-aliasing filter can also be eliminated due to the anti-aliasing property of CT modulators. On the other hand, CT ADC have their own problems, such as jitter sensitivity and excess loop delay.

In this thesis, the state-of-the-art of CT modulator is reviewed. The problems in the design of CT ADCs are analyzed and solutions to them are described. The theory, design and implementations of CT modulator will also be reviewed.

An Implementation of a Reliable Broadcast Scheme for 801.11 Using Network Coding
Forward Error Correction and retransmission are two approaches used to reliably broadcast data in a network with poor quality of service. Taking some assumptions, it has been suggested that a retransmission based reliable broadcasting scheme using network coding should in theory provide an increase in bandwidth efficiency by combining packets as they are retransmitted. In this thesis, we remove those assumptions by providing two algorithms to implement the previously proposed scheme. These two algorithms differ in a way that allows them to compare the tradeoffs between two different methods of packet loss notification. We test these two algorithms over several parameters and provide insights into the cause of their performance attributes.

Data Processing and Visualization for Anomaly Detection in Web-Based Applications
Web applications are popular attack targets. Misuse detection systems use signature databases to detect known attacks. However, it is difficult to keep the database up to date with the rate of discovery of vulnerabilities. They also cannot detect zero-day attacks. By contrast, anomaly detection systems learn the normal behavior of the system and monitor its activity to detect any deviations from the normal. Any such deviations are flagged as anomalous. This thesis presents an anomaly detection system for web-based applications. The anomaly detection system monitors the attribute value pairs of successful HTTP requests received by webserver applications and automatically creates parameter profiles. It then uses these profiles to detect anomalies in the HTTP requests. Customized profiles help reduce the number of false positives. Automatic learning ensures that the system can be used with different kinds of web application environments, without the necessity for manual configuration. The results of the detection are also visualized, which enable the system administrator to quickly understand the state of the system and respond accordingly.

Training Design and Power Allocation for Closed-Loop Multi-Antenna Systems with Limited Feedback
The multi-input and multi-output (MIMO) wireless systems have been being an active research area in recent years because of their large multiplexing gain and diversity gain comparing with single-antenna systems. Although non-coherent MIMO systems do not need the channel knowledge at the receivers, but they incur high decoding complexity which limits their applications. Coherent MIMO systems need channel knowledge at the receivers and sometimes at the transmitters (e.g., in transmitter beamforming, precoding, power loading) to explore above gains. Three topics are presented in this proposal. First, in a practical beamforming system where the feedback channel is not error-free, the scheme to minimize the error effect is proposed. Second, in a training-based closed-loop MIMO system where the receiver acquires channel knowledge by training and feedbacks the channel knowledge to the transmitter, the optimal training design is proposed to maximize a lower bound of closed-loop capacity. At last, as the further work of the research, the time-selective block fading MIMO channel model will be considered where the training design will be optimized by taking the correlation between consecutive blocks into account.

Performance Evaluation of Hybrid Peer-to-Peer System for Streaming
Finding an efficient way of distributing content in Peer-to-Peer (P2P) networks has become important with the growing popularity of media streaming applications. Video multicast applications rely on the efficiency of content distribution from a single source to multiple receivers where one source streams a video to a large number of destination nodes through an overlay multicast tree consisting of peers.

The topologies of these P2P networks do not make efficient use of the bandwidth of the participating nodes. The Hybrid Peer-to-Peer architecture (Hypp) provides an application layer mesh that exhibits near optimal throughput by having all nodes, including the leaves, contribute to the overall system throughput. This project presents the experimental results of a real world P2P system based on the Hypp topology deployed on PlanetLab nodes. The Hypp architecture achieves near optimal throughput while provides scalability, low delay and bandwidth fairness among peers.

Automated Model Parameter Extraction for Noise Coupling Analysis in Silicon Substrates
An automated process, requiring the fabrication of a small set of test structures, efficiently extracts the coefficients of Z-parameter based macromodels. The extraction process has been validated for both heavily and lightly doped substrates and can be applied to a variety of technologies. After the parameters of a macromodel have been extracted, the model can be used to quickly and accurately calculate the equivalent substrate network connecting an arbitrary number of contacts.

This automated extraction process has been integrated into the Cadence DFII environment to provide a seamless flow for substrate noise analysis.

Efficient Power Conversion Interface Circuits for Energy Harvesting Applications
Power harvesting from the environment for powering micro-power devices have been increasing in popularity. These types of devices can be used in embedded applications or in sensor networks where battery replacement is impractical. In this dissertation, different methods of harvesting power from the environment are explored to obtain alternatives for battery powered devices. Some of the most popular energy extraction methods used in these devices is radio frequency (RF) and piezoelectric energy extraction.

New power conversion circuits to interface to a piezoelectric micro-power generator have been fabricated and tested. Circuit designs and measurement results are presented for a half-wave synchronous rectifier with voltage doubler, a full-wave synchronous rectifier and a passive full-wave rectifier circuit connected to the piezoelectric micro-power generator. The measured power efficiency of the synchronous rectifier and voltage doubler circuit fabricated in a 0.35-μm CMOS process is 88% and the output power exceeds 2.5-μW with a 100-kΩ, 100-nF load. The two full-wave rectifiers (passive and synchronous) were fabricated in a 0.25-μm CMOS process. The measured peak power efficiency for the passive full-wave rectifier circuit is 66% with a 220-kΩ load and supplies a peak output power of 16-μW with a 68-kΩ load. Although the active full-wave synchronous rectifier requires quiescent current for operation, it has a higher peak efficiency of 86% with a 82-kΩ load, and also exhibits a higher peak power of 22-μW with a 68-kΩ load which is 37% higher than the passive full-wave rectifier.

Current RF-powered devices are typically inductively coupled and extract their energy from the near field while operating within a few inches of the radiating source. Longer operating distances, exceeding 10 meters, is desired for a broader set of applications including distributed sensor networks. This dissertation describes an efficient method for far field power extraction from RF energy to enable long-distance passively powered sensor networks. An RF-DC power conversion system is designed to efficiently convert far-field RF energy to DC voltages at very low received power. Two passive rectifier circuits are designed in the TSMC 0.25μm mixed-signal CMOS process and the antenna for the system is printed on a 4-layer FR4 board with a carefully controlled trace impedance. A high-Q resonator is used with a matching network to passively amplify the input voltage to the rectifier. At the circuit level, floating gate transistors are used as rectifying diodes to reduce the diode threshold loss in voltage rectification and therefore increase the rectifier efficiency.

With the 36-stage rectifier, the system can attain maximum efficiency of 60% at 3 meters distance and can rectify input voltages as low as 50mV and has passive voltage gain of 6.4. This system operate at 2.5V at received power as low as 5.5μW (-22.6 dBm), corresponding to 44 meters operating distance. For distances of 15 meters, 1 volt DC is measured with 0.3μA load current at 906 MHz.

PPTAssist, A tool help user reuse slides and a framework for applying information retrieval techniques over presentation documents
Over time, individuals and workgroups accumulate large collections of presentations. Few create new presentations from scratch, rather they use past presentations as templates and cut and paste previously created components on slides into a new presentation.
However, frequently this process is costly and error-prone. Tools that help create presentations more effectively and efficiently by reusing past presentations could substantially decrease the time we spend creating presentations. Yet currently there are no tools to provide good support for this specific activity. PPTAssist is a tool developed to promote reuse activities by extracting meaning association between slides in a given document corpus and recommend possible reusable slides for given authoring tasks. It is also designed to serve as a framework for comparing retrieval techniques for recommending slides. In the project, different associating and ranking algorithm are tested and the implementation techniques involving the construction and design aspects are discussed. During the talk, you will also see a live demo of the PPTAssist software.

Improved Design Techniques for Analog and Mixed Circuits
Although the digital revolution can realize many of past analog components in the digital forms, our world is surrounded with analog signals such as voice, temperature, etc. The bridge between these two worlds is one of key performance limitations among overall systems and it includes analog filters and data converters.

This thesis studies two design techniques with respect to the improvement of the performances of the bridge circuits; one is an implementation of the delta-sigma A/D converter with a new architecture and another is a proposed correlated double-sampling technique for continuous analog filters. A circuit implementation for the new architecture converter is proposed and implemented in AKM 0.18µm CMOS technology. The test results show that the modulator achieves 72dB of SNDR from the 1.8 V supply voltage. A newly proposed correlated double sampling technique compensates the gain error of a high-Q Tow-Thomas filter which originates from the op-amp imperfections. The gain error is reduced to 0.6dB from 2.5dB with the correlated double sampling technique.

Supporting the Learning Process of Open Source Novices: An Evaluation of Code and Project History Visualization Tools
Active participation and collaboration of community members are crucial to the continuation and expansion of open source software projects. Researchers have recognized the value of community in open source development and studied various aspects of it including structure of communities, motivations for participation, and collaboration among members. However, the majority of previous work is devoted to active contributors and little is known about newcomers to open source projects. In an attempt to bringing more attention to these potential contributors to open source and supporting their joining process by enhancing their initial learning experience, we investigated the information needs of those who are considering joining an open source project as developers and use of software in fulfilling the needs and providing information that are important to perform software development/maintenance tasks. Our controlled experiment has revealed that the tools and resources available from current open source projects are lacking in providing information that is embedded in development artifacts such as discussion archives, trackers, and source code.

Difficulty obtaining such information may have a negative impact on newcomers' motivation on learning and further their engagement in activities. Our investigation of information visualization in support of learning suggests that providing visual information to newcomers may alleviate the difficulties associated with managing a large amount of information and enhance their learning experience.

PhD Oral Preliminary Examination - Igor Vytyaz
Major Professors: Kartikeya Mayaram, Un-Ku Moon
Committee: Luca Lucchese, Pavan Kumar Hanumolu, David Lee
GCR: William Warnes

Design-oriented steady-state and sensitivity analysis and optimization of autonomous circuits
Fast analysis and optimization techniques for autonomous circuits are presented in this thesis. New design-oriented large-signal circuit analyses and the small-signal sensitivity analyses for oscillators have been developed. The design-oriented analyses efficiently find values of circuit parameters that result in a desired circuit performance given by a set of equality constraints. These analyses enable formulation a more compact optimization problems. The new sensitivity analysis for oscillators provides feasible search directions, such that at each step in an optimization procedure the design equality constraints are satisfied.

Efficient VLSI Architectures for MIMO and Cryptography Systems
Multiple-input multiple-output (MIMO) communication systems have recently been considered as one of the most significant technology breakthroughs for modern wireless communications, due to the higher spectral efficiency and improved link reliability. The sphere decoding algorithm (SDA) has been widely used for maximum likelihood (ML) detection in MIMO systems. It is of great interest to develop low-complexity and high-speed VLSI architectures for the MIMO sphere decoders.

The first part of this dissertation is focused on the low-complexity and high-speed sphere decoder design for the MIMO systems. It includes the algorithms simplification, and transformations, hardware optimization and architecture development. Specifically, we propose the layered reordered K-Best sphere decoding algorithm and dynamic K-best sphere decoding algorithm, which can significantly improve the detection performance or reduce the hardware complexity. We also present the efficient K-Best sorting architecture, which greatly simplifies the sorting operation of the K-Best SDA. In addition, we introduce the early-pruning K-Best SD scheme, which eliminates the unlikely candidate at early decoding stages, thus saves computational complexity and power consumptions. For the conventional sphere decoder design, we develop the parallel and pipeline interleaved sphere decoder architecture, which considerably increases the decoding throughput with negligible extra complexity. Finally, we design the efficient radius and list updating units for the list sphere decoder, which increases the speed of obtaining the new radius and reduces the complexity for generating the new candidate list.

The wireless communication technologies are widely used for the benefits of portability and flexibility. However, the wireless security is extremely important to protect the private and sensitive information since the communication medium, the airwave, is shared and open to the public. Cryptography is the most standard and efficient way to protect the securities.

The second part of this thesis is thus dedicated to the high-speed and efficient architecture design for the cryptography systems including ECC and Tate pairing. We propose an efficient fast architecture for the ECC in Lopez-Dahab projective coordinates. Compared with the conventional point operation implementations, the point addition and doubling operations can be significantly accelerated with reasonable hardware overhead by applying parallel processing and hardware reusing. Moreover, we develop a complexity reduction scheme and an overlapped processing architecture for the Tate pairing in characteristic three. The proposed architecture can achieve over 2 times speedup compared with conventional sequential implementations for the Duursma-Lee and Kwon-BGOS algorithms.

Re-finding Documents Using Provenance Information with TaskTrail
Recent research suggests that file attributes such as title, location, size, and time of last use are poorly remembered by users, yet these attributes are arguably the most frequently utilized by existing desktop search tools. This paper describes a search tool which takes an entirely new approach, enabling users visualize the relationships between documents and thereby re-find documents via their provenance relationships to other documents.

Activity Recognition in Desktop Environments
Knowledge workers are struggling in the information flood.

There is a growing interest in intelligent desktop environments which help knowledge workers organize their daily life. Intelligent desktop environments allow the desktop user to define a set of "activities" that characterize the user's desktop work. These environments then attempt to identify the current activity of the user in order to provide various kinds of assistance. TaskTracer is one of these efforts. Our previous work on activity recognition has shown some fairly good results. However, possible improvements do exist. First, there could be different levels at which we can describe an activity, and until now we have only focused on the highest level. Second, our current predictor follows the standard "bag-of-words" approach, and rich relational information was ignored.

To address the above issues, we propose to classify activities into three levels: "task" as in TaskTracer, workflow, and operation. In this proposal, we concentrate on the two higher levels of activity -- "task" and "workflow" -- and we propose an activity recognition solution for each of them. To recognize tasks, we propose a discriminative training approach. This approach employs relational features and adopts the Passive-Aggressive Algorithm (PA) for online training. To recognize workflows, we formally describe the problem and analyze its complexity. The data consists of interleaving instances and is relational in its nature. These pose a challenge for the recognition and make it necessary to do some approximations. We propose several possible solutions based on different approximation assumptions. In the end, we discuss the research contribution and present the research plan.

Satellite Image Processing and Web-Based Services Implementation
The objective of this paper is to document the image-processing pipeline and visualization tools used to organize and process data returned from the High Resolution Imaging Experiment (HiRISE) and the context camera (CTX) on board the Mars Reconnaissance Orbiter (MRO). The image processing tools ISIS and GDAL were used to convert raw data to various image formats as requested by mission scientist. A web-based interface was created to make the images publicly available throughout JPL. The centralized imagery server enables users to access a consistent set of imagery data through a standard interface, and to provide a single repository to update when new images become available.

Novel Design and Implementation of a Permanent Magnet Linear Tubular Generator for Ocean Wave Energy Conversion
The world's energy consumption is growing at an alarming rate and the need for renewable energy is apparent now more than ever.

Estimates have shown that optimization of the extraction of energy from the ocean could significantly aid the world's quest for sustainable and affordable energy services for all. From small power data buoys to generating power for coastal communities, everyone stands to benefit from the technological optimization of ocean wave energy devices. This thesis explores the design and implementation of a novel permanent magnet linear generator for direct drive ocean wave energy extraction point absorber buoys. The design optimizes the armature and magnet sections of a permanent magnet linear tubular generator (PMLTG) for the purposes of maximizing the energy conversion efficiency while minimizing cogging forces. Cogging forces in a linear generator influence power fluctuations and hydrodynamic performance of the wave energy extraction system. Implementation techniques involving the construction and mechanical design aspects are included.

Joint Maximum Likelihood Estimation of Timing and Frequency Offset in OFDM System
OFDM system is a popular multi-carrier modulation scheme that is robust to frequency selective fading, highly spectral efficient and capable of achieving high data rate. However, it is very sensitive to timing and frequency offset. This report proposes a cyclic-prefix based joint Maximum Likelihood estimation of timing and frequency offset. Our method does not need a training sequence and thus can significantly reduce transmission overhead. The simulation results also show our estimator has a much better performance than the conventional method.

Power Reduction of MPEG Video Decoding for Mobile Multimedia Systems
The purpose of this thesis is to explore methods which can reduce the power dissipation of a mobile system while decoding MPEG video. MPEG decoding is a microprocessor intensive process that makes heavy use of both the L1 and L2 caches as well as main memory. The heavy load placed on the system during the MPEG decoding process results in large dynamic power losses caused by both the execution of instructions and the flow of data into and out of the caches and main memory. To reduce the power dissipation of the system during MPEG decoding, multiple techniques were applied to control the flow of data and make the decoding process more efficient. The system was simulated with different L2 cache sizes to determine which sizes resulted in the best power improvements while maintaining acceptable performance levels.

A fast IDCT algorithm was implemented to improve the efficiency of the decoder during the computationally heavy IDCT phases. Finally, selective caching was introduced to the system to further reduce the traffic between the caches and main memory. These techniques were simulated on the Sim-Panalyzer simulator using a similar system configuration to one found in a typical mobile media device. These methods coupled with proper L2 cache sizing produced power reductions of 50-60% over the baseline system.

High Speed, High Resolution Track-and-Hold and Efficient Parallel Delta-Sigma ADC
This work presents an efficient implementation of a parallel delta-sigma analog-to-digital converter. The parallel architecture uses four delta-sigma based channels, each consisting of a 2-1-1 MASH architecture, as well as a shared 8-bit pipelined quantizer. The architecture provides high speed and high resolution with flexibilty to dynamically adjust resolution and bandwidth and to perform some basic signal processing at the front end. This converter achieves 15 bit SNR over a 12.5 MHz signal bandwidth, with an oversampling of 4X in simulation. The chip is designed in a TSMC 0.25um process. The design of high-speed, high-resolution track and hold blocks can be a limiting factor in the data converter design. Also presented will be a high-speed, high-resolution closed loop track and hold in 0.18um SiGe BiCMOS technology. The architecture presented provides 15 bit linearity and >100MS/s while reducing the input loading by a factor of 10X compared to conventional closed-loop designs.

Mining Behavioral Patterns from HCI Data
The main aim of the project is to find users strategies and behavior patterns from the human computer interaction log data. We focus on extracting general strategies from the log data and associating them strategies with users gender and problem solving success. The HCI application in our study is the gender HCI project, which uses a problem-solving prototype software called forms/3. We applied sequential pattern mining to the log data and obtain user action patterns while using the software. We find that the obtained individual patterns fail to provide general strategies used by the users and are redundant in structure. This led us to examine different ways of clustering the patterns. The group of clusters obtained helped us find interesting strategies that appear to be related to users gender and success in problem solving.

Visualization and Analysis of Species Diversity in the HJ Andrews Experimental Forest
Often current scientific research suffers from an effective presentation environment. Sometimes software tools will be developed only for specific research datasets and are often impractical for others. This paper explores the use of Google Earth as a visualization environment and discusses the author's project for generating Kml and related files. Kml files describe geospatial information and define how it is presented within Google Earth. As a proof of concept, two distinct datasets from the HJ Andrews Experimental Forest are used as the basis for this paper. The first dataset is on spatial distribution of exotic plant species. The second dataset is on the spatial and temporal distribution of moths. Variations in the presentation and analysis of each dataset, along with the project implementation details will be discussed.

Kinematic and Cyclostationary Parameter Estimation for Co-Channel Emitter Location Applications
The problem of locating a signal source, or an emitter, has many civilian and military applications, such as communication regulations enforcement, military reconnaissance, and search-and-rescue operations. Many of the most widely used emitter location methods rely on the accurate and robust estimation of the differential time delay, or time-difference-of-arrival (TDOA), and the differential Doppler shift, or frequency-difference-of-arrival (FDOA), between signal replicas arriving at two spatially separated receivers. There are many conventional methods for estimating TDOA and/or FDOA. However, these methods are unable to produce unbiased TDOA and FDOA estimates when multiple emitters are located spatially close to each other. In many cases, the spatial proximity at which the conventional methods fail is still too large to ignore for precision emitter location applications. This problem is made even more difficult when the signals from the emitters share the same regions of the spectrum at the same time.

When spatially close emitters overlap spectrally and temporally, robust TDOA and FDOA estimation is difficult, and accurate emitter location jointly requires both the estimation of TDOA, or FDOA, or both, as well as the estimation of a signal parameter that can be used to separate the signal-of-interest (SOI) from a signal(s)-not-of-interest (SNOI) that are within the receiver's field of view. The signal separation parameter selected depends on the type of signal modulation. In this thesis, the signals of interest are bauded signals. The separation methodology for such signals is cyclostationarity with parameterization by cyclic frequency. Based on this assumption, a new three-dimensional joint estimation method for TDOA, FDOA, and cyclic frequency parameters, called alpha cross ambiguity function (alphaCAF), has been developed to exploit signal modulations with cyclostationary properties. By exploiting cyclostationarity, alphaCAF can produce separate unbiased TDOA and FDOA estimates that will in turn yield reliable geolocation estimates for precision emitter location applications even when severe interference causes conventional methods to fail. In this thesis the alphaCAF parameter estimation (TDOA, FDOA, Cyclic Frequency) algorithm is introduced along with a complete analysis of its performance compared to conventional estimators. A connection is also made between the alphaCAF algorithm and the additional steps needed to perform an emitter location technique.

Applying Machine Learning to Enterprise Alert Management
The network infrastructure for an enterprise system consists of many servers and hardware. Most modern day electronics are far from perfect and failures are common within a huge network. Enterprise systems records alerts (i.e. errors, failures, warnings, etc.) from the network into a database. These alerts in enterprise systems are growing in complexity and magnitude. The massive amounts of alerts reported are far too large to be managed by humans and usually only a subset is inspected. This project consists of three parts: first we performed an exploratory analysis of enterprise alert data to see if patterns existed. Next we created an alert simulator based on a mixture of Markov chains. Finally we extended the raw data with temporal features and performed an analysis using machine learning algorithms in WEKA.

Enhancing WebGen5 with Access Control, AJAX Support, and Editable-and-Insertable Select Form
WebGen is a software tool for generating Web scripts automatically for a Web-based database application. In this project, access control, AJAX support, and editable-and-insertable table mechanisms were added to WebGen. With our access control mechanism, an access-control level can be specified for each table. In access control level 1, for example, a user can read any records, and a logged-in user can insert records and update and delete the records inserted by her.

There are five access control levels. WebGen now can generate an AJAX server-side PHP script that retrieves, based on a given value, one or multiple records from the database. The given value may be selected from a dropdown list in a form, and the retrieved value or values can be set in an input element or in a select element as options, respectively.

With an editable-and-insertable select form, a user can now read, insert, update, and delete multiple records in a table at one time.

Correlated Level Shifting
Correlated level shifting (CLS) is introduced as a technique to provide true rail-to-rail performance while simultaneously reducing errors from finite op-amp gain. CLS is a technique similar to output referred correlated double sampling, except the sampling process stores the signal on a capacitor instead of the error. There is no speed penalty. CLS is applied to a 20M Sample/S, 11mW (analog) pipelined A/D converter which achieves 10.5 ENOB operating 16mV from rails using an op-amp with 30dB loop gain and 0.9V supply. Future research directions will also be discussed.

Interface effects in oxide based thin-film transistors
The goal of this research is to study the effect of different dielectric materials at the channel-gate dielectric interface of oxide based thin-film transistors. Oxide based thin-film transistors provide a feasible route towards large-scale electronics, flexible electronics and transparent electronics due to high performance at plastic compatible processing temperatures. Materials used for oxide based electronics and figures of merits will be discussed.

Finding and Using Chokepoints in Stratagus
This paper describes a method for finding areas of interest on a two-dimensional grid map used in the real-time strategy engine Stratagus. The method involves discovering chokepoints where through all simulation agents must pass. Using a set of tunable parameters, a full set of chokepoints are located. The redundant and useless chokepoints are then filtered out of the set. The resulting chokepoints can then be used to create a graph of the high-level map structure. The method used to cull less-useful chokepoints is presented. Secondarily, two algorithms were developed that help decide at which chokepoints a limited number of defensive structures may be placed for the greatest benefit. The results of a series of tests are given that show that these algorithms are valuable: tower placements based on both the optimal and greedy implementations, built on the maximum network flow of the resultant graph, perform markedly better than random placement.

Further, the framework (also by the author) used in this project is dissected.

Architecture Design of Multiplexed Incremental Analog-to-Digital Converters
Analog-to-Digital Data Converters (ADCs) used in instrumentation and measurements often require high absolute accuracy, including excellent linearity and negligible dc offset. Incremental data converters (IDCs) provide a solution for such measurement applications. Since IDCs are essentially delta-sigma (ΔΣ) converters with reset operation before each conversion, they retain most of the advantages of conventional ΔΣ converters, and yet they are capable of offset-free and accurate conversion.

Most of the previous research on incremental converters is for single-channel and dc signal applications, where they can perform extremely accurate data conversion with more than 20-bit resolution. In this thesis, the operation and the performance of IDCs in both frequency and time domain is analyzed. Design techniques for implementing multiplexed IDCs to convert narrow bandwidth ac signals are discussed too. It incorporates the operation principles, modulator topologies, digital filter design and signal-to-noise ratio optimization methodology. The theoretical analysis is verified by simulation results.

Effective Decision-Theoretic Assistance through Relational Models
Building intelligent computer assistants has been a long-cherished goal of AI. Many intelligent assistant systems were built and fine-tuned to specific application domains. In this work, we develop a general model of assistance that combines three powerful ideas: decision theory, hierarchical task models and probabilistic relational languages. We use the principles of decision theory to model the general problem of intelligent assistance. We use a combination of hierarchical task models and probabilistic relational languages to specify prior knowledge of the computer assistant. The assistant exploits its prior knowledge to infer the user's goals and takes actions to assist the user. We evaluate the decision theoretic assistance model in three different domains including a real-world domain to demonstrate its generality. We show through experiments that both the hierarchical structure of the goals and the parameter sharing facilitated by relational models significantly improves the learning speed of the agent. Finally, we present the results of deploying our relational hierarchical model in a real-world activity recognition task.

Analysis and Design Techniques for Sampling Linearity and Nano-Joule Temperature Sensing
A novel model predicts tracking nonlinearity (NL) in the form of harmonic distortion (HD) for weakly NL (i.e. SFDR>30dBc) first order open-loop sampling circuits. The mechanisms for the NL are exponential settling, amplitude modulation, phase modulation and discrete-time modulation. The model demonstrates that HD typically increases at 20 dB per decade over most standard operating ranges and is a function of input frequency, sampling bandwidth, input amplitude, the sample rate and component nonlinearity. Application of the model is reduced to the equivalent of frequency-independent nonlinearity analysis over this range, requiring only a Taylor series expansion of the NL time constant. Design insight is given for common MOS switch types, revealing a high correlation between HD and bandwidth. The first method to quantify the tradeoff between thermal noise (SNR) and linearity (SFDR) for sampling circuits is presented. Measured HD2, HD3, HD4 and HD5 versus frequency at multiple sample rates of a Sample and Hold test chip fabricated in a 0.25µm 1P5M CMOS process and Spectre simulation results support the findings. The results broadly apply to switched capacitor circuits in general and sampling circuits specifically, regardless of technology.

Passive (battery-free) wireless sensor networks present numerous design challenges, particularly energy consumption, at both the system and sensor level. Energy budgets for such a wireless sensor are orders of magnitude lower than one powered by a battery. Thus, the overriding design goal of this work is to achieve the minimum possible energy consumption for a temperature to digital converter, which consists of a temperature sensor and an analog to digital converter (ADC). Employing a ratio-metric measurement principle that eliminates the need for a reference voltage and its buffer, a temperature to digital converter design is proposed that theoretically improves upon the best energy consumption per conversion reported to date for temperature to digital converters by two orders of magnitude to roughly one nano-joule per conversion. It operates on a 1V supply and consumes 1.4µA at a 20kHz sample rate. Each seven bit conversion is achieved in 10 clock cycles using successive approximation programmable gain amplifier architecture with only a single amplifier and comparator. The proposed design has been fabricated in a 0.18µm SiGe BiCMOS process and is in the early stages of characterization.

Thin-film Inorganic Solar Cells
The primary objective of this thesis is to explore new absorber and p-type window layer materials for thin-film solar cell applications. Material investigations include iron silicon sulfide (Fe2SiS4) and barium copper tin selenide (BaSn2SnSe4) for absorber applications, and barium copper tellurium fluoride (BaCuTeF) for p-type window layer applications. Experiments involving the insertion of BCTF window layers into cadmium telluride (CdTe) and copper indium gallium diselenide (CIGS) thin-film solar cells is elucidated via interface assessment using modern Schottky barrier and heterojunction theory. The experimental work performed benefits from the availability of a new custom designed electron beam thin-film deposition system. Assistance in the construction and installation of this tool in the design of a load lock and the development and implementation of an operating procedure for this tool are described.

Permanent Magnet Helical Screw Drive
Engineering solutions for linear to rotary conversion and rotary to linear conversion typically rely on the use of mechanical devices to convert linear thrust to rotating torque and visa vi. These conventional conversion methods require lubrication, have wear surfaces exposed to high loading, require preventative maintenance, and require periodic replacement of worn components. Friction, mechanical wear, and lost efficiency are a consequence of using such conversion systems. Such limitations can be overcome by replacing the mechanical thrust converting elements with permanent magnetic forces. This thesis explores the replacement of a screw-nut thread engagement with permanent magnet threads. By replacing the frictional elements (threads) of a ball screw system (for example) with permanent magnets, it is conceivable that a highly reliable and efficient linear to rotary system can be employed.

Such a system will be explored for the purpose of ocean wave energy conversion but may be extended to other applications. Models using analytic calculations, finite element analysis, and physical experiments are explored to investigate the feasibility of such a system. Full scale applications and system integration to wave energy converter buoys are important considerations for such a device and these aspects of system design will also be explored.

Continuous Time Input ADCs
Analog-to-digital converters (ADCs) convert analog signals into digital format. Processing signals in digital format has become cheaper as digital circuits shrink in size. This has led to widespread availability of mobile devices from ipods to cell phones.

Some applications demand higher performance ADCs-posing a real challenge for I.C. designers. Such applications are cell phone base-stations and medical imaging. When designing such devices, designers strive to add as little noise and as little distortion as possible to the signal.
This becomes increasingly more difficult at higher sampling rates and higher signal bandwidths. Oftentimes such devices consume considerable power -ruling out battery powered applications.

Continuous time input Pipelined ADCs solve a number of challenges present in state-of-the-art ADCs :-

1. High performance pipeline ADCs burn a lot of power due to op-amp requirements 2. Sampling distortion 3. Bootstrap switches are required for good distortion 4. High performance pipeline ADCs occupy significant silicon area 5. Limited input voltage range 6. Driving pipeline ADCs from the outside world is difficult 7. An anti-alias filter is typically required in front of the ADC

Such an ADC is composed of a continuous time front end that resolves some bits in the continuous time domain followed by a conventional back-end pipeline ADC. The key aspect of the continuous time front end is a circuit that estimates the signal ahead of time. This enables a continuous time ADC front end that is power efficient and eases the challenges listed above.

An automated web crawl methodology to analyze the online privacy landscape
Protecting end-users privacy and building trust are the two most important factors needed to support the growth of ecommerce. The increased dependence on the Internet for a wide variety of daily transactions causes a corresponding loss in privacy for many users, as virtually all websites collect data from users directly or indirectly while performing business with them.

In this thesis I have used a web crawler named “iWatch” which serves as an instrument to collect basic statistics on the state of privacy, security, and data-collection practices on the web. I have looked at several interesting practices, and ways of examining the data. This thesis is also meant to serve as a point for reflection and discussion about which practices to observe, and how the raw data from such a system can and should be evolved and made available to a wider audience.

The purpose of this thesis is to show web-crawling is a valid approach to mass data collection over the internet with the aim of predicting privacy practices and analyzing how they have evolved in the last three years in terms of geography, legislation, risks, biases and flows.

Finally I demonstrate methods to show how to control bias while collecting data, and I propose a probabilistic mathematical model to limit the depth of search to achieve wider breadth for web crawling techniques in the future.

A Probabilistic Model for Anomaly Detection in Remote Sensor Streams
Remote sensors are becoming the standard for observing and recording ecological data in the field. Such sensors can record data at fine temporal resolutions, and they can operate under extreme conditions prohibitive to human access. Unfortunately, sensor data streams exhibit many kinds of errors ranging from corrupt communications to partial or total sensor failures. This means that the raw data stream must be cleaned before it can be used by domain scientists. In our application environment-the H.J. Andrews Experimental Forest-this data cleaning is performed manually. This thesis introduces a Dynamic Bayesian Network model for analyzing sensor observations and distinguishing sensor failures from valid data for the case of air temperature measured at a 15-minute time resolution. The model combines an accurate distribution of seasonal, long-term trends and temporally localized, short-term temperature variations with a single generalized fault model.
Experiments with historical data show that the precision and recall of the method is comparable to that of the domain expert.

The Commentator Information System: understanding journalists' needs to overcome cognitive load and navigation issues
Nowadays, sports events are a significant part of the every-day entertainment with local, national, and international championships. A lot of money is invested by broadcasting companies to attract new and more viewers, acquire broadcasting rights, or send entire crews on site to cover such events. Journalists are among the few who go on site. To perform their job and make appealing live commentaries, journalists need a lot of information about athletes, past and live results, records, etc. The Commentator Information System (CIS) is the on-site tool used by journalists for these purposes, and made available by the organizers.

The CIS is an LCD touch-screen device that allows users to retrieve sports data by selecting specific buttons on the interface: final or heat results, intermediate times, weather conditions, medal standings, etc. There is one CIS per event; hence the system can cover dozens of different disciplines (e.g. during the Olympic Games) at the same time.

There has been research conducted on how to improve TV and online viewers’ experience during sports events but nothing, as of today, about improving journalists’ work environment. Moreover, their work conditions are very stressful; if they make mistakes in their statements, it can have negative consequences on their career. Thus, the CIS has to be reliable from both a system and usability perspective.

Through this study I found important navigation issues and some missing information concerns. I observed that journalists rely heavily on their own notes and not much on the CIS. I discovered, users do make mistakes and have difficulties multitasking under this type of pressure. Finally, I noticed some gender differences in the task performances when users have to find information in the CIS.

Gender differences in end-user debugging strategies
There has been little prior research reporting strategy usage in end-user problem solving, and even lesser using gender as a factor. Without this type of information, end-user programming systems cannot know the “target” at which to aim, if they are to support male and female end-user programmers’ debugging. As a background to the thesis, an experiment was conducted by our group members, where the participants were given a post session questionnaire that had an open-ended question about what debugging strategies they adopted in finding and fixing errors. It was found that among the mentioned strategies, testing and code inspection had significant statistical differences among male and/or female success groups. This thesis’s goal is the investigation of the behavioral evidence of the two primary strategies, testing and code-inspection using gender as a factor. Using quantitative and qualitative methods, we analyzed the two strategies reported, and looked for relationships among participants’ strategy choices, gender, and debugging success. Our results indicate that males and females debug in quite different ways, and the debugging strategies that worked well for the males were not the same ones that worked well for the females. Our results also reveal that tools currently available to end-user debuggers may be especially deficient in supporting debugging strategies used by females.

At frequencies exceeding 1-2 GHz, the reactive nature of a silicon substrate must be accounted in the substrate network models used in substrate coupling simulation. High-frequency substrate models, containing reactive components, must be validated through high-frequency network analyzer measurements.

Prior fabricated test fixtures have been modified to enable high-frequency (up to 20 GHz) network parameter measurements of a 0.35 µm CMOS heavily-doped silicon substrate through an off-chip probing scheme. The performance of the test fixture and the measurement deembedding procedure has been evaluated, and suggestions for future improvements are presented.

New probing scheme is proposed to enable high-frequency network parameter measurements of a silicon substrate. The design of the test structures and the deembedding procedure has been validated through extensive simulations in HFSS.

Explaining Debugging Strategies to End-User Programmers
There has been little research into how end-user programming environments can provide explanations that could fill a critical information gap for end-user debuggers – help with debugging strategy. To address this need, we designed and prototyped a video-based approach for explaining debugging strategy, and accompanied it with a text-only approach. We then conducted a qualitative empirical study with end-user debuggers. The results reveal the influences of the explanations on end-user debuggers’ decision making, how users reacted to the video versus textual media, and the information gaps the explanations closed. The results also reveal issues of particular importance to explanations of this type.

Low-Complexity High-speed VLSI Design of Low-Density Parity-Check Decoders
Low-Density Parity-check (LDPC) codes have attracted considerable attention due to their capacity approaching performance over AWGN channel and highly parallelizable decoding scheme. They have been considered in a variety of industry standards for the next generation communication systems. In general, LDPC codes achieve outstanding performance with large codeword lengths (e.g., N>1000 bits), which lead to a linear increase of the size of memory for storing all the soft messages in LDPC decoding. In the next generation communication systems, the target data rates range from a few hundred Mbit/sec to several Gbit/sec. To achieve those very high decoding throughput, a large amount of computation units are required, which will significantly increase the hardware cost and power consumption of LDPC decoders. LDPC codes are decoded using iterative decoding algorithms. The decoding latency and power consumption are linearly proportional to the number of decoding iterations. A decoding approach with fast converge speed is highly desired in practice.

This thesis considers various VLSI design issues of LDPC decoder and develops efficient approaches for reducing memory requirement, low complexity implementation, and high speed decoding of LDPC codes. We propose a memory efficient partially parallel decoder architecture suited for quasi-cyclic LDPC (QC-LDPC) codes using Min-Sum decoding algorithm. We