Metal Fill Considerations for On-Chip Interconnects and Spiral Inductors
Variability in circuit performance due to process defects is a major concern in integrated circuit (IC) fabrication. Advanced IC manufacturing processes employ Chemical-Mechanical Polishing (CMP) for planarization of oxide and metal layers. CMP defects result in variations in the oxide and metal topographical profile. To reduce these topographical variations, electrically non-functional (dummy) metal features are added in low metal density regions. These metal fills degrade the performance of on-chip interconnects and components, and the overall circuit due to the additional electrical parasitics. Therefore, it is important to characterize the parasitic effects of metal fill on critical structures such as interconnects and spiral inductors.

This thesis presents a study of the impact of metal fill placement, size, and shape on the electrical performance of representative on-chip transmission line structures and spiral inductors. We separate the electric and magnetic effects of different metal fill designs by studying their impact on parasitic capacitance and eddy-current loss. The study is done through simulation using a commercial full-wave electromagnetic simulator and measurement of a test chip fabricated in a 180nm BiCMOS process, and is supported through theoretical considerations. For a reduction in fill size of about 90% while keeping the same metal density, we find a significant reduction in parasitic microstrip capacitance and microstrip resistance by about 30% compared to the larger fill size. Similarly, a 70% decrease in fill size provides an improvement of about 13% in measured quality factor of a representative spiral inductor design. Using octagonal metal fill shapes reduces the parasitic microstrip capacitance by about 45% and microstrip resistance by about 13% compared to square shapes with the same metal density. Furthermore, measurement results for a spiral inductor show larger impact on the quality factor and self-resonance frequency for off-plane metal fill compared to in-plane metal fill.

Low Power Design Techniques for Analog-to-Digital Converters in Submicron CMOS
Advances in process technologies have led to the development of low-power high speed digital signal processing blocks that occupy small areas. However, the design of analog building blocks, especially analog-to-digital converters (ADCs), becomes complex and power-inefficient with each advance in process node due to decreasing swing and intrinsic gain. This work introduces circuit techniques that enable the design of low-complexity power-efficient ADCs in submicron CMOS. The techniques include replacing the power-hungry opamp in integrators, used in delta-sigma modulators, with low power zero-crossing-based ones. Also proposed is an enhanced correlated level shifting technique that allows the use of simple low gain opamps to realize high performance pipelined ADCs. Fabricated prototypes of the delta-sigma and pipelined ADCs, along with their simulation and measurement results, are employed to discuss the effectiveness of the techniques in achieving compact low-power designs.

On achievable throughput region of single-hop wireless networks using network coding
We investigate the achievable throughput region of single-hop wireless networks via network coding. First, we propose a hybrid network coding technique to be used at a wireless base station (BS) to increase the throughput efficiency for both broadcast and unicast transmissions. The main idea is to implement appropriate mixing of flows at the BS and demixing of flows at the receivers. In this way, we show that, theoretically the throughput region can be increased. Second, we investigate the achievable throughput region for scenarios involving prioritized transmissions. Prioritized transmissions are useful in many multimedia networking applications where the transmitted data have an inherent hierarchy such that a piece of data at one level is only useful if all the pieces of data at all the lower levels are present. We show that using our proposed technique, the achievable throughput region for the prioritized transmissions can be substantially enlarged. Simulations and theoretical analysis have been provided to verify our proposed techniques.

A Recurrent Neural Network Implementation Using the Graphics Processing Unit
Recurrent neural networks (RNNs) are a powerful tool in learning time-varying signals which feed-forward neural networks cannot. One of the major weaknesses of RNNs are their high order of complexity. Because of this, in situations when training basic feed-forward neural networks would take on the order of days, training RNNs would take on the order of weeks. The graphics processing unit (GPU) is capable of executing a large number of similar tasks in parallel. As a result, certain tasks can benefit from a large speed increase when implemented on the GPU. This thesis explores an implementation of RNNs on the GPU.

A Self-Calibrated, Reconfigurable RF LNA
Modern wireless Systems-on-Chip's (SoCs), such as mobile handsets, sensor networks, and mm-wave systems, integrate an entire RF system on a single CMOS chip. Such highly complex systems require significant on-chip digital signal processing to help improve the performance on highly sensitive, analog/RF components. The IC market being competitive, the ability to achieve first pass silicon success is crucial, due to very high processing and testing time cost. Unfortunately, the ability to achieve first-pass silicon success is becoming increasingly more difficult, due to higher system complexity, higher frequency of operation, increased performance requirements, and higher process skews.

This thesis presents a dual mode 2.4/2.0 GHz, reconfigurable RF Low Noise Amplifier (LNA) using on-chip peak detection and calibration, to mitigate the deleterious effects of process, voltage and temperature (PVT) variations. The LNA can reconfigure its input impedance matching, as well as its gain. On-chip detection of optimal input/output impedance matching is performed using an amplitude peak detector rather than a conventional power detector, improving the parasitic loading of the sensitive input node. A low power, robust maximum peak point calibration scheme is proposed that calibrates the LNA to the resonant frequency of interest. Measurement results show that the calibration of the LNA improves the input matching (S11) by a maximum of 5 dB, and the power gain (S21) by 3dB, while not significantly degrading the Noise Figure (NF).

Discriminative Methods for Complex Multi-Object Tracking
In this work, we discuss the problem of tracking multiple objects in video. In particular, we focus on discriminative techniques for training multi-object tracking systems, with our motivation stemming from the growing body of empirical and theoretical evidence suggesting that discriminative methods are superior to generative ones when enough data is available. The discussion in this work is driven by the challenging problem of tracking players in low-resolution video of American football, but it also applies more generally. Our end goal is to propose several concrete applications of discriminative training methods to complex multi-object visual tracking problems. In meeting this goal, we review recent research related to multi-object tracking and to discriminative methods relevant to this problem. We also discuss already completed work that is foundational to our proposals.

Design Techniques for Driving Light Emitting Diode
Increasing popularity of cellular phones with integrated cameras in the recent past has led to major improvements in the image quality. However, integration of new features, such as mobile email, video streaming, MP3 etc. tend to put the limitation on image quality as camera phone designers struggle to manage multiple features while maintaining healthy battery life time.

In this research, a novel efficient power management scheme for camera phones with flash for better image/video quality is discussed. A prototype power management circuit comprising of a 2 MHz Buck-and-Boost DC-DC converter driving up to 1.2A flash light emitting diode (LED) in 500nm CMOS process is implemented. The converter achieves high efficiency over the entire Li-On battery voltage range of 3.0 to 5.2 V by operating in buck, buck-and-boost and boost mode based on the input/output voltage and load current requirements. The converter operates with a peak efficiency of 83% and 87% at 1.2A and 0.6A LED currents, respectively.

Polarization diversity and directional communication in 60 GHz wireless networks
It is well known that multipath effects cause inter-symbol interference (ISI) for high-speed signaling and ultimately limit the achievable data rate at any frequency band. Due to the unique characteristics of electromagnetic waves in the 60 GHz band, well established methods that are used to mitigate ISI cannot be used in this high-data rate license free spectrum. In this thesis, we study several different methods to tackle this issue and provide solutions for establishing efficient wireless links that can provide several Gbps data rate. Specifically, we show that polarization diversity, when used with the proposed topology detection algorithm reduces the multipath in 60 GHz wireless channel and increases the error-performance of the network. We also provided a direction detection algorithm for directional communications in 60 GHz, which is proven to be effective in reducing multipath and increasing spatial diversity. Finally, we propose a double directional channel model for 60 GHz channel as a modification to IEEE 802.15.3c channel model to include the effects of directional antennas both on the transmitter and the receiver side.

Fabrication and Characterization of p-type CuO/ n-type ZnO Heterostructure Gas Sensors Prepared by Sol-Gel Chemical Processing Techniques
Increased interest in the field of sensor technology stems from the availability of an inexpensive and robust sensor to detect and quantify the presence of a specific gas. Bulk p-CuO/n-ZnO heterocontacts have been shown to exhibit the necessary sensitivity and selectivity characteristics, however, low interfacial CuO/ZnO contact area and poor CuO/ZnO connectivity limits their effective use as gas sensors.

The phase equilibrium between CuO and ZnO exhibits limited solubility. By exploiting this concept, a CuO/ZnO mixed solution is formed by combining CuO and ZnO precursors using wet chemical techniques (sol-gel). Thin films fabricated using this mixed solution exhibit a unique CuO/ZnO microstructure such that ZnO grains are surrounded by a network of CuO grains. This is highly beneficial in gas sensing applications since the CuO/ZnO heterostructure interfacial area is considerably increased and is expected to enhance sensing characteristics.

This work builds on previous research by Dandeneau et al. (Thin film chemical sensors based on p-CuO/n-ZnO heterocontacts, Thin Solid Films, 2008). CuO/ZnO mixed solution thin films are fabricated using the sol-gel technique and subsequently characterized. X-ray diffraction (XRD) data confirms the phase separation of ZnO and CuO. Scanning electron microscopy (SEM) as well as energy dispersive spectroscopy (EDS) reveals a network of ZnO grains amidst a matrix of CuO grains. Optical and electrical characterization provides material parameters used to construct an energy band diagram for the CuO/ZnO heterostructure. Aluminum interdigitated electrodes (IDEs) are patterned on the thin film and gas sensing characteristics in the presence of oxygen and hydrogen is investigated. Optimization of the electrode geometry is explored with the aim of increasing the sensitivity of the sensor in the presence of hydrogen.

Realistic Three Dimensional Simulation of Spraying Water
The ability to create realistic looking three-dimensional game environments has approached a level that can make it difficult to determine if a scene is computer generated, or an actual photograph. However, some effects, such as spraying water from a hose, have not been able to match the same level of realism. Mismatched levels of realism can ruin the immersive experience that really draw people into a virtual world, such as a game. This project explores various techniques for creating a realistic simulation of water spraying from a hose at interactive rates. A few of the techniques are examined in detail, resulting in several prototype implementations.

Skeletal Parameter Estimation in a Live Motion Capture Session
Preparing an actor for an optical motion-capture session is time-consuming task. By ensuring that enough motion capture data is collected during the session, the cost of multiple preparations can be avoided. A typical post-process after a motion capture session is to fit the motion capture to a skeletal structure. This project implements a paper published by Kirk et al. entitled “Skeletal Parameter Estimation from Optical Motion Capture Data” (2005), which describes a method to compute this skeletal structure. However, this project goes a step further, and allows users to process the data during, rather than after a live session. This allows studio operators to verify that enough data has been collected to compute skeletal parameters before terminating the session. Furthermore, operators may assist the automated approach, interactively correcting any errors produced between steps of the skeletal generation process.

Applying Machine Learning for Prediction, Recommendation, and Integration
This dissertation explores the idea of applying machine learning technologies to help computer users find information and better organize electronic resources, by presenting the research work conducted in the following three applications: FolderPredictor, Stacking Recommendation Engines, and Integrating Learning and Reasoning.

FolderPredictor is an intelligent desktop software tool that helps the user quickly locate files on the computer. It predicts the file folder that the user will access next by applying machine learning algorithms to the user's file access history. The predicted folders are presented in existing Windows GUIs, so that the user's cost for learning new interactions is minimized. Multiple prediction algorithms are introduced and their performance is examined in two user studies.

Recommender systems are one of the most popular means of assisting internet users in finding useful online information. The second part of this dissertation presents a novel way of building hybrid recommender systems by applying the idea of Stacking from ensemble learning. Properties of the input users/items, called runtime metrics, are employed as additional meta features to improve performance. The resulting system, called STREAM, outperforms each component engine and a static linear hybrid system in a movie recommendation problem.

Many desktop assistant systems help users better organize their electronic resources by incorporating machine learning components (e.g., classifiers) to make intelligent predictions. The last part of this dissertation addresses the problem of how to improve the performance of these learning components, by integrating learning and reasoning through Markov logic. Through an inference engine called the PCE, multiple classifiers are integrated via a process called relational co-training that improves the performance of each classifier based on information propagated from other classifiers.

Indexing Web 2.0 Applications
Current search engines (Google, Yahoo, MSN etc.) do not index Web 2.0 applications. This is primarily because Ajax applications consist of a set of states (unlike traditional webpages) which are generated by the user through actions such as click, focus, blur etc. events. By saving these DOM states we can index information obtained from dynamically generated web content. To prevent indexing of duplicate DOM states, a Tree Edit Distance algorithm known as Fast Match Edit Script has been implemented.

Learning Ranking Functions for Beam Search
Beam search is commonly used to help maintain tractability in large search spaces at the expense of completeness and optimality. Here we study supervised learning of linear ranking functions for controlling beam search. The goal is to learn ranking functions that allow for beam search to perform nearly as well as unconstrained search, and hence gain computational efficiency without seriously sacrificing optimality. In this proposal, we consider the ranking function that is represented as a linear combination of features. The first part of this proposal is to study the problem of learning weights for a given set of features. We formally define the weight learning problem and present a theoretical analysis, in terms of its computational complexity and the convergence of various learning algorithms. Next, we present an empirical evaluation of applying weight learning in automated planning, showing that our approach is often able to outperform an existing state-of-the-art planning heuristic as well as a recent approach to learning such heuristics. Finally, we develop algorithms to automatically inducing features, in the form of action-selection rules. Our initial empirical results have shown significant promise in a number of planning domains.

Efficient Training and Feature Induction in Sequential Supervised Learning
Sequential supervised learning problems arise in many real applications. This dissertation focuses on two important research directions in sequential supervised learning: efficient training and feature induction.

In the direction of efficient training, we study the training of conditional random fields (CRFs), which provide a flexible and powerful model for sequential supervised learning problems. Existing training algorithms for CRFs are slow, particularly in problems with large numbers of potential input features and feature combinations. In this dissertation, we describe a new algorithm, TreeCRF, for training CRFs via gradient tree boosting. In TreeCRF, the CRF potential functions are represented as weighted sums of regression trees, which provide compact representations of feature interactions. So the algorithm does not explicitly consider the potentially large parameter space. As a result, gradient tree boosting scales linearly in the order of the Markov model and in the order of the feature interactions, rather than exponentially as in previous algorithms based on iterative scaling and gradient descent. Detailed experimental results are provided to evaluate the performance of the TreeCRF algorithm and possible extensions of this algorithm are discussed.

We also study the problem of handling missing input values in CRFs, which has been rarely discussed in the literature. Gradient tree boosting also makes it possible to use instance weighting (as in C4.5) and surrogate splitting (as in CART) to handle missing values in CRFs. Experimental studies of the effectiveness of these two methods (as well as standard imputation and indicator feature methods) show that instance weighting is the best method in most cases when feature values are missing at random.

In the direction of feature induction, we study the search-based structured learning framework and its application to sequential supervised learning problems. By formulating the label sequence prediction process as an incremental search process from one end of a sequence to the other, this framework is able to avoid complicated inference algorithms in the training process and thus achieves very fast training speed. However, for problems where there exist long range dependencies between the current position and future positions, at each search step, this framework is unable to exploit these dependencies to make accurate predictions. In this dissertation, a multiple-instance learning based algorithm is proposed to automatically extract useful features from future positions as a way to discover and exploit these long range dependencies. Integrating this algorithm with maximum entropy Markov models yields promising experimental results on both synthetic data sets and real data sets that have long range dependencies in sequences.

A Force Control Algorithm for a Wave Energy Linear Test Bed
Researchers at Oregon State University, focusing on the development of ocean wave energy converters, have designed and installed a unique linear test bed to aid in the characterization of these converters. Under the original control scheme, the linear test bed follows a position profile and is limited in its ability to replicate the forces a wave energy converter would experience in the ocean. To overcome these limitations, a force control algorithm has been developed to better simulate the hydrodynamic effects between an ocean wave and a wave energy converter device. This thesis presents the design and implementation of the force control algorithm on the linear test bed.

Modeling Spintronics Devices in Verilog-A for use with Industry-Standard Simulation Tools
As the semiconductor industry works to integrate increasingly more "non-CMOS" devices onto CMOS ICs, compact model development has become an important step in the circuit/system verification tool flow. This research focuses on modeling the physical phenomena that occurs when changing the magnetization state of different spintronic devices such as GMR spin valves, toggle MRAM bits and magnetic tunnel junctions (MTJs). The various torques responsible for magnetization change are modeled in separate Verilog-A blocks which are assembled together to create a particular device. All device compact models have electrical I/O and are being developed to provide accurate device terminal behavior when used in a circuit simulation environment with standard CMOS circuits.

WiMAX and simulated performance (based on NCW)
The US military is evaluating the capabilities of emerging technologies based on IEEE 802.16 standard as a potential commercial off-the-shelf solution to support the communication requirements of the future war.

In the last few years, development in military and telecommunication industries has focused on an intensive use of broadband systems, which are characterized by high quality features. In order to use broadband systems, new technologies with high transmission abilities have been designed. Broadband wireless access has become the best way to meet escalating military and business demands for a rapid internet connection and integrated communication. Based on IEEE 802.16 standard, WiMAX allows for an efficient use of bandwidth in a wide frequency range, and can be used as last miles solution for broadband access.

NCW(Network Centric Warfare) is the most important system in the recent military environment. All assets should be interactively combined in real time. Especially ground and aviation forces like infantry, UAVs(Unmanned Arial Vehicle), Attack Helicopters.

This thesis gives an overview of WiMAX standard and studies the performance of WiMAX over the multipath channel fading, and how to apply WiMAX to aviation communication.

Bird Species Recognition Using Hidden Markov Models
Recognition of bird species by analyzing their song recordings is a well-studied problem. This work tries to analyze and compare two different approaches to classify bird species by analyzing their recordings. Bird songs consist of features that have temporal structure and these features can be used to distinguish one species from another; Hidden Markov Models are best suited for modeling the temporal structure of these recordings.

The two different approaches involved here use Hidden Markov Models to capture the temporal structure in the sound recordings. The difference in the two approaches is in their smallest indivisible unit that is used to create the features. One method takes the frames inside each chunk as the smallest unit and the other method takes each element as a unit, a sequence of frames or elements will form a feature vector for the chunk.

The feature vectors are then used to train the Hidden Markov Model; a separate HMM is trained for every species. Both these methods have shown that there is a strong temporal structure to the recordings, and give an accuracy result of around 88% correct prediction.

Topological Analysis, Visualization, and Design of Vector Fields on Surfaces
Analysis, visualization, and design of vector fields on surfaces have a wide variety of major applications in both scientific visualization and computer graphics. On the one hand, analysis and visualization of vector fields provide critical insights to the flow data produced from simulation or experiments of various engineering processes. On the other hand, many graphics applications require vector fields as input to drive certain graphical processes. This thesis addresses the vector field related processing for both visualization and graphics applications.

Vector field topological analysis provides the qualitative (or structural) information of the underlying dynamics of the given vector data, which helps the domain experts identify the critical features and behaviors efficiently. In this thesis, I introduce a more complete vector field topology called Entity Connection Graph (ECG) by including periodic orbits, an essential component in vector field topology. An efficient periodic orbit extraction technique is introduced and incorporated into the algorithm for ECG construction. The analysis results are visualized using the improved evenly-space streamline placement with all separation features being highlighted. This is the first time that periodic orbits can be extracted in surface flows. Through applications to engine simulation datasets, I demonstrated how the extracted topology helps engineers interpret the flow data that contains certain desirable behaviors which indicate the ideal engineering process.

Accuracy is typically of paramount importance for visualization and analysis tasks. However, the trajectory-based vector field topology approaches are sensitive to small perturbation such as error and noise which are contained in the given data and introduced during data acquisition and processing. This makes rigorous interpretation of vector field topology and flow dynamics difficult. To overcome that, I advocated the use of Morse decomposition to define a more reliable vector field topology called Morse Connection Graph (MCG). In particular, I presented the pipeline of Morse decomposition of an input vector field. A technique based on the idea of t-map was introduced to produce desirable fine Morse decompositions of vector fields. To address the issue of slow performance of the global t-map framework, I described a hierarchical MCG refinement framework. It enables the t-map approach to be conducted within a Morse set of interest which greatly reduces the computation cost and leads to faster analysis. My work on Morse decomposition has set a benchmark for stable analysis of vector field topology which will invoke the investigation of other similar data analysis problems such as scalar field and tensor field analysis.

The techniques of time-independent vector field design have been well-studied. However, there is little attention on the problem of time-varying vector field design on surfaces. This thesis addresses this problem by developing a design system that allows the creation and modification of time-varying vector fields on surfaces. More detailed, I present a number of novel techniques to enable efficient design over important characteristics in the vector field such as singularity paths, pathlines, and bifurcations. These vector field features are used to generate a vector field by either blending basis vector fields or performing a constrained optimization process. Unwanted singularities and bifurcations can lead to visual artifacts, and we address them through singularity and bifurcation editing. We demonstrate the capabilities of our system by applying it to the design of two types of vector fields: orientation field and advection field for the application of texture synthesis and animation.

Wideband High-Resolution 4th Order Single Amplifier Biquad (SAB) Based Hybrid Delta-Sigma Modulator in 0.13um CMOS
There is a large demand in the recent Mobile Communication and Wireless Broadband systems for high-performance analogue-to-digital converters (ADCs) that have a wide bandwidth (BW>9MHz) and high data rate (>100Mbps). A delta-sigma ADC is known as a power-efficient ADC when high resolution (>12b) is required. The continuous-time (CT) delta-sigma ADC is favored over its discrete-time (DT) competitor when the application requires high bandwidth or low power dissipation.

A 4th-order 4-bit single stage hybrid delta-sigma ADC with a novel Single Amplifier Biquad (SAB) based loop filter is presented. Utilizing this idea, the N-th order CT loop filter of the modulator has only N/2 number of amplifiers and feed-forward branches instead of N in the conventional one. In addition to decreasing power consumption by reducing the number of amplifiers, the proposed scheme enables modulator to have a DT adder which consumes less power instead of the conventional CT adder. With a 130-nm CMOS technology, simulations indicate that the proposed ADC can achieve a 13 bit resolution with 10 MHz signal bandwidth and power dissipation lower than 16mW.

Document classification by learning multiple non-redundant codebooks with word clustering
The problem of document classification has been widely studied in machine learning and data mining. In document classification, most of the popular algorithms are based on the bag-of-words representation. Due to the high dimensionality of the bag-of-words representation, significant research has been conducted to reduce the dimensionality via different approaches. One such approach is to learn a codebook by clustering the words. Most of the current word- clustering algorithms work by building a single codebook to encode the original dataset for classification purposes. However, this single codebook captures only a part of the information present in the data. This thesis presents two new methods and their variations to construct multiple non-redundant codebooks using multiple rounds of word clusterings in a sequential manner to improve the final classification accuracy. Results on benchmark data sets are presented to demonstrate that the proposed algorithms significantly outperform both the single codebook approach and multiple codebooks learned in a bagging-style approach.

Information Foraging in Debugging
Programmers spend a substantial fraction of their debugging time by navigating through source code, yet little is known about how programmers navigate through source code. With the continuing growth in size and complexity of software, this fraction of time is likely to increase, which presents challenges to those seeking both to understand and address the needs of programmers during debugging.

In this dissertation, we investigated the applicability a theory from another domain, namely information foraging theory, to the problem of programmers’ navigation during software maintenance. The goal of our investigation was to determine the theory’s ability to provide a foundational understanding that could inform future tool builders aiming to support programmer navigation.

To perform this investigation, we first defined constructs and propositions for a new variant of information foraging theory for software maintenance. We then operationalized the constructs in different ways and built three executable models to allow empirical investigation of our theory. We developed a simple information-scent-only model of navigation, a more advanced model of programmer navigation, named Programmer Flow by Information Scent (PFIS), which accounts for the topological structure of source code, and PFIS 2, a refinement of PFIS that maintains an up-to-date model of source code on the fly and models information scent even in the absence of explicit information about stated goals.

We then used the models in three empirical studies to evaluate the applicability of information foraging theory to this domain. First, we conducted a lab study of 12 IBM programmers working on a bug report and feature request. Second, we conducted an analysis of issues and revisions collected from Sourceforge.net. Finally, we collected programmer navigation behavior, revisions and issues from a field study of programmers working in various groups at IBM.

All three models predicted programmers’ navigation behavior in some way, including where programmers allocated their time among patches, where programmers went, or where programmers made changes to fix defects. PFIS was able to predict individual programmer navigation behavior as well as a team could predict individual programmer navigation behavior, and even better than any individual could predict any other individuals’ program navigation behavior. PFIS 2 was able to predict programmer navigation behavior incrementally, taking into account programmers’ evolving understanding of the goals, and succeeded even without explicit descriptions of the initial goals.

Other models of programmer behavior, such as those based on hypotheses, information scent alone or topology alone, were less effective at predicting programmer navigation behavior.
These results indicate that information foraging theory can model programmer navigation behavior, and imply that tools based on the principles of information foraging theory will be able to predict subsequent navigation behavior and potentially assist where programmers should go to make changes to fix bugs.

An Implementation of Graphcut Textures: Image and Video Synthesis Using Graph Cuts
This project is an implementation of “Graphcut Texture: Image and Video Synthesis Using Graph Cuts” by Vivek Kwatra et al [2003], who developed a novel method for texture synthesis of images and videos. In order to synthesize a new texture of an image or video, blocks are chosen from an input image or video and pasted into an output. The new technique, called graph cut, is used to determine the best match among blocks at the output without considering the size of the block. The advantage of graph cut over the dynamic programming technique is that it is suitable not only for images but also videos. The authors also introduced the technique, called patch placement and matching, to find the patches with regardless of the size of a patch. The results show the synthesized images with stochastic and structured texture properties, video synthesis, and images synthesized from multiple input images. In this project, I provided an implementation of this paper and discuss a number of issues encountered during this implementation.

PhD Oral Preliminary Examination - Omid Rajaee
Major Advisor: Un-Ku Moon
Committee: Gabor Temes, Pavan Hanumolu, Bechir Hamdaoui
GCR: Nathan Gibson

High Precision, Low OSR Oversampling A/D Converters
An important design challenge for oversampling ADCs is to obtain higher BW without losing accuracy. Higher BW for oversampling ADCs can be achieved by reducing oversampling ratio (OSR). However, maintaining accuracy at reduced OSR generally requires complex and power hungry architectures.

In this work, two unique methods for implementing High precision, low OSR oversampling ADCs are presented. These architectures combine efficiency of pipeline ADCs with noise shaping properties of delta-sigma modulators to achieve high accuracy at very low OSRs (OSR < 8) without imposing stringent requirements on circuit components.

These ideas are supported by various circuit/system level simulations and measurements.

Analysis and Optimal Sizing for an Energy Storage System for Wind Farm Applications
Modern wind energy is the technology of choice with a short payback period for increasing renewable energy portfolios. Bonneville Power Administration (BPA), a United Stated power authority in the Pacific Northwest expects to increase their wind energy capacity from 2,000 megawatt to 6,000 megawatts within the next five years. Currently BPA uses their vast hydroelectric resources to counteract the variability of wind energy, but the control of hydroelectric power is somewhat limited by water and fish conditions on the Columbia River. As the integration of wind energy continues to increase, the variability of wind energy on the power system must be addressed. Large scale energy storage systems such as pumped hydro, compressed air, and flow cell batteries are viable technologies to support high wind energy integration. This thesis presents a method for obtaining optimal energy capacity and power rating for an energy storage system for wind farm support.

Wireless Network Coding for Multi-User Networks
Network Coding (NC) refers to the notion of mixing information from different flows at intermediate nodes in the network, and it has been shown to achieve the network throughput capacity. In this work, we investigate NC theories and practical techniques for improving throughput and reducing delay of wireless networking applications. Specifically, the work will focus on theoretical analysis of NC benefits and limitations as well as design of NC-based practical protocols for improving performance in a wireless access network such as Wi-Fi or WiMax. There are three main following contributions.

First, we propose a NC-based retransmission protocol for broadcasting information from a wireless base station to multiple users in a wireless access network. The proposed NC protocol exploits the special property of wireless transmissions that users in proximity, can listen to each other's transmissions to code the packets in such a way to increase every user throughputs. Both theoretical analysis and simulation results show a significant throughput gain when using the proposed NC protocol over the standard ARQ protocol.

Second, we propose a NC-based packet scheduler at a wireless base station for delivering multimedia streams, particularly scalable video streams to multiple users in a wireless access network. We formulate the NC-based packet scheduler problem in the framework of Markov Decision Process (MDP) in which, packet delay, inter-dependency of packets, and different visual contributions of packet types are taken into account, to optimize for the overall visual qualities. We describe an optimal scheduler for transmitting scalable video streams to a small number of users. For a large number of users, we propose a heuristic, simulation-based algorithm for finding the near-optimal transmission policy.

Third, we introduce Random Network Coding (RNC) techniques. More specifically, we present a prioritized RNC scheme for multimedia transmission for multiuser in a wireless access network. We then study a real-world implementation of RNC. We describe the step-by-step design of encoding and decoding modules of RNC and measure their computational rates.

Using provenance to aid document re-finding
In the field of Human-Computer Interaction, provenance refers to the complete history and genealogy of a document. Provenance can be useful in identifying related resources, such as different versions of the same document or resources used in the creation of a new document.

Though methods of provenance collection and applications for provenance have been studied, no studies have documented the frequency of provenance events in typical computer use. We conducted a study of knowledge workers at Intel and used event-logging software to track provenance events in the workplace over several weeks. We also interviewed knowledge workers to evaluate provenance data as an effective cue for document recall. Our data shows that provenance relationships are quite common, and provenance helped users recall more about their documents and understand the context of their workflows. Through a detailed analysis of the challenges facing knowledge workers, their typical work practices, and the utility of provenance, we argue that visualizing provenance can be useful in desktop search.

Development of Biomimetic Control Strategies for the Optimal Use of Renewable Sources and Energy Storage Systems
In the year 2007, the worldwide energy consumption accumulated to a total of 16.5 billion MWh. While the resources of conventional energy production cause environmental damage, renewable energy sources like solar or wind power offer a solution to substitute for coal or nuclear generated power. Countries like Denmark and Spain have shown that a high penetration of renewable power is possible; however, the production shifts from a demand-driven production to a supply-driven electricity production. This causes the problem that energy could be available while the demand is low or vice versa.

Energy storage could be a solution to this challenge.

This thesis investigates how an envisioned storage system for a wind park in northern Oregon could be controlled in order to optimize its capacity. Two biomimetic strategies, neural network and fuzzy logic control, were implemented and later optimized by a genetic algorithm to increase the profit from storing the electric energy in the storage unit.

Even though the optimization with genetic algorithms leads to improvements in the performance of the neural network and fuzzy logic controller, the results show that biomimetic controllers only perform as good as a simple, unconstrained power split controller. Both controllers are tested with several months of wind and price data.

Functional Simulation of the Task-Scheduling Language PLEXIL
An interdisciplinary study into the theory of design decisions has yielded a model for tracking design changes in hardware/software systems, but it still needs to be applied to a larger system to test its efficiency at tracking important data. This thesis creates an implementation of PLEXIL, a language in development at NASA for controlling various hardware systems, as a testbed for applying the model of design decisions. This PLEXIL system is embedded in the functional language Haskell to take advantage of its static typing and lazy evaluation, and it accurately follows the defined semantics defined by NASA. The external world representation in this thesis improves upon NASA’s current simulator through the definition of new data types for more dynamic runtime behavior.

Electrically Tunable Thin Film Inductors Based on Synthetic Antiferromagnet (SAF) Cores
The objective of this thesis is to provide an initial demonstration of the feasibility of implementing electrically tunable on-chip inductors based on synthetic antiferromagnet (SAF) cores. Such a demonstration is successfully achieved in presenting the electrically tunable magnetic thin film cores through permeability modulation. A tuning range (relative change in permeability) of 35 % can be achieved at 800Hz using patterned NiFe/Ru/NiFe SAF structures. By incorporating such tunable cores into on-chip inductors, it will enable a variety of new circuit approaches such as phase shifters, and range-shifting VCO's.

Magnetic Bead Detection with Ferromagnetic Resonance for Use in Immuno-Biosensor Application
The objective of this thesis is to introduce and demonstrate a novel magnetic bead detector based on inductive detection at the ferromagnetic resonance (FMR) frequency for use in bio-sensing applications. Detection ability is demonstrated through theoretical arguments, numerical computer simulations, and experimental characterization of a micro-fabricated detector. The detector is composed of two uniplanar rf waveguides (coplanar waveguide and slotline) terminated together at a short-circuit junction, which serves as the sensitive area. Experimental characterization of a micro-fabricated junction gives a signal ranging between 1µV/V and 12µV/V, depending on the number of beads at the junction as well spatial distribution of the beads. The location around the tips of the CPW were shown to be the most sensitive. A more complex rf circuit design was created employing the detection junction, and detection of magnetic beads was successfully shown at rf frequencies around 6 GHz in this configuration. Due to lack of FMR characterization data for magnetic beads in the literature, several varieties of magnetic beads were characterized using a CPW transmission line to determine FMR properties. Finally, successful detection of magnetic beads was demonstrated in a system-level integration experiment employing the detector junction in combination with microfluidics and bio-chemical surface modifications.

Urban Operation Mobility Model
A Mobile Ad-hoc NETwork (MANETs) is collection of wireless mobile nodes without network infrastructures or centralized administration. Although MANETs can be used in many applications, such as mobile Internet, military communication, and disaster relief networks, a number of challenges remain. These include routing, medium access control, security, scalability, energy efficiency, mobility, etc. Therefore, in order to study the viability of large-scale MANETs, researchers rely on wireless network simulators to test new ideas. Wireless network simulations require several important parameters, such as routing protocols, mobility models, and data traffic models. Among these, developing realistic mobility models is crucial for accurately evaluating the performance MANETs.

There are many models that emulate mobility of users. The most representative are entity and group mobility models. In a battlefield, mobility patterns of military units are different than mobility patterns of civilians. Thus, a special group mobility model is needed to appropriately simulate military operations on the battlefield.

This thesis proposes a new group mobility model for military urban operation called Urban Operation Mobility Model (UOMM). In UOMM, the group moves along a road and employs group partitioning for new missions and allows for merging at the specific locations. UOMM also employs a time delay to model soldiers encountering and overcoming obstacles during a missions. Finally, we studied the impact of three mobility models UOMM, RPGM, and RWP, on different routing protocols.

Some Communication Algorithms for Gaussian and Eisenstein-Jacobi Networks
Interconnection networks plays important role in designing high performance computers. Recently two new classes of interconnection networks based on the concept of Gaussian and Eisenstein-Jacobi integers are introduced. In this research, efficient routing and broadcasting algorithms for these networks are developed. Furthermore, constructing edge disjoint Hamiltonian cycles in Gaussian networks are also investigated. Some resource placement methods for Eisenstein-Jacobi networks are also studied.

Monte-Carlo Planning for Probabilistic Domains
We examine Monte-Carlo solutions for problems in probabilistic planning, a branch of planning that includes environments and/or action models with stochastic properties. We have developed a diverse family of algorithms from combining existing Monte-Carlo simulation techniques, such as UCT, Hindsight Optimization and Sparse Sampling. Our efforts have resulted in a policy for Klondike Solitaire that wins more than 36% of games -- to our knowledge the first published bound of any kind for Klondike. We also present our work in the Fire, Rescue and Emergency Response domain and extend our Monte-Carlo methods to address the problem of constrained policies. We propose additional work to combine value function learning with these methods, and describe the projected impact our work will have in the field of robabilistic planning.

Ultra Low Capacitance RFIC Probe
The high speed low capacitance probe presented here is a flexible tool for internal node testing on Radio Frequency Integrated Circuits (RFIC) or high frequency digital ICs. The probe utilizes the mutual capacitive coupling between two wires. In this case, a tungsten whisker and the inner conductor of a coaxial cable form a capacitor, enabling extremely low probing (loading) capacitance. The probe can be modeled, to the first order, as a capacitor that provides differentiating action of an input signal. Viewing the derivative of the probed signal, rise time can be observed directly. Through the use of probe calibration and Fourier transforms the probed signal can be re-created. Probe calibration develops a transfer function enabling re-creation of time domain signals.

Access Control for a User Participatory Web-Based GIS Application Implemented with Drupal 6.x
A user participatory web-based application allows its users to contribute and share information. Supporting geographical information by such an application has become important. Furthermore, features for content management, web-mapping, and social networking need be integrated with proper access control.

In this project, we describe an implementation of access control for a user participatory web-based GIS application. The application should be able to support groups of users and friends of users so that proper information sharing can occur among group members or friends.

We are now developing a user participatory web-based GIS application that allows its users to find and share information on fishing in Oregon. The application is implemented with Drupal 6.x for content management and with contributed modules for social networking, such as Organic Groups and User Relationships. We also created custom modules to handle new content types that support location-based data. In order to enable access control for contents of custom content types, the custom modules utilize access control mechanisms implemented by the Drupal Core and the modules for social networking.

A Novel Linear Generator for Wave Energy Applications
With the increasing effort to identify alternative methods of energy generation, extraction of ocean energy has gathered a large interest. Research and industry have begun considering wave energy as the next new alternative energy. When looking further into energy extraction via the point absorber technology, a direct drive linear generator most appropriately converts the vertical wave motion into electrical energy. With considerations of long term reliability in an ocean environment as well as design to product cost, a longitudinal flux variable reluctance permanent magnet generator is the ideal generator topology. This paper identifies the reasons behind the selection of this particular generator topology for a point absorber. It provides a description of the generator topology and operation before continuing with the details as to the development of a variable reluctance permanent magnet generator with specifically known design constraints. The paper further describes the implementation, testing, and results of such a device, while touching on considerations to take into account throughout the design process.

Incremental A/D Converters
Two new techniques are proposed for incremental A/D converters (IDC): a new analysis and optimization technique for the system design and a new D/A converter (DAC) calibration technique for the double sampling scheme. A third-order incremental ADC is designed to verify the proposed techniques.

MS FINAL ORAL EXAM - Mizuki Kagaya
Major Professor: Eugene Zhang
Committee: Sinisa Todorovic, Yuji Hiratsuka
GCR: Michael Scott

Painterly Rendering Using Space-Time Varying Style Parameters
Automatic painterly rendering systems have been proposed but they opted for selecting a single style to generate paintings from images, which lacks the ability of creatively using multiple styles to focus important objects and deemphasize unimportant part of the scenes. We provide a multi-style painting framework to address this issue as well as techniques to enhance the quality of the painting.

To summarize, this project makes the following contributions.

• Multi-style painting framework: A canvas is considered as a collection of non-overlapping regions that correspond to objects or background of input images and videos. Within each region stroke orientation can be specified and user-depened painting style parameters can be assigned. Those assigned attributes are also used to denevalues for regions with any attribute unspecied.
• Color-based stroke ordering: By relating the drawing order of strokes to their colors, one can create more coherent paintings rather than a randomly assigned order.
• Implicit renderer: We propose a renderer with a different perspective from existing explicit approaches. Brush strokes are simultaneously generated by advecting images of seeds of the strokes in a way that they are repeatedly morphed according to stroke orientation.
  

The Dynamic Speculation and Performance Prediction of Parallel Loops
General purpose computer systems have seen increased performance potential through the parallel processing capabilities of multicore processors. Yet this potential performance can only be attained through parallel applications, thus forcing software developers to rethink how everyday applications are designed. The most readily form of Thread Level Parallelism (TLP) within any program are from loops. Unfortunately, the majority of loops cannot be easily multithreaded due to inter-iteration dependencies, conditional statements, nested functions, and dynamic memory allocation. This dissertation seeks to understand the fundamental characteristics and relationships of loops in order to assist programmers and compilers in exploiting TLP.

First, this dissertation explores a hardware solution that exploits (TLP) through Dynamic Speculative Multithreading (D-SpMT), which can extract multiple threads from a sequential program without compiler support or instruction set extensions. This dissertation presents Cascadia, a D-SpMT multicore architecture that provides multi-grain thread-level support. Cascadia applies a unique sustainable IPC (sIPC) metric on a comprehensive loop tree to select the best performing nested loop level to multithread. Results showed that Cascadia can extract large amounts of TLP, but ultimately, only yielded moderate performance gains. The lack of overall performance gains exhibited by Cascadia were due to the sequential nature of applications, rather than Cascadia's ability to perform D-SpMT.

In order to fully exploit TLP through loops, some loop level analysis and transformation must first be performed. Therefore, second contribution of this dissertation is the development of several theoretical methodologies to aid programmers and auto-tuners in parallelizing loops. This work found that the inter-iteration dependencies have a two-fold effect on the loop's parallel performance. First, the performance is primarily affected by a single, dominant dependency, and it is the execution of the dominant dependency path that directly determines the parallel performance of the loop. Any additional dependencies cause a secondary effect that may increase the execution time due to relative dependency path differences. Furthermore, this study analyzes the effects of non-ideal conditions, such as a limited number of processors, multithreading overhead, and irregular loop structures.

Supply-Noise Mitigation Techniques for Phase-Locked Loops
Phase-Locked Loops (PLLs) are essential building blocks in many communication systems and all large digital systems. Ring oscillator based PLLs are used in these applications to achieve the wide-tuning range with minimal area penalty. These PLLs are very sensitive to supply noise mandating techniques to mitigate the noise on the supply and achieve the desired jitter performance. In this work, a supply-regulated PLL employing split-tuned architecture is proposed that decouples the trade-off between power consumption in regulator and supply-noise rejection performance. The prototype PLL fabricated in a 0.18um digital CMOS process operates from 0.5 to 2.5GHz. At 1.5GHz, the proposed PLL achieves 1.9ps long-term r.m.s jitter and a worst-case supply-noise sensitivity of -28dB (0.5rad/V), an improvement of 20dB over conventional solutions, while consuming 2.2mA from a 1.8V supply.

PLLs are also used in clock and data recovery (CDR) circuits in which the supply noise increases the bit-error rate (BER). The proposed PLL architecture is used in a dual-loop CDR to achieve a low BER in the presence of supply-noise. An on-chip jitter-tolerance measurement technique is also proposed to measure jitter-tolerance without the use of expensive measurement apparatus. Techniques to reduce power consumption in the CDR are presented to minimize the overallpower consumption in the CDR.

Partial Network Coding with Cooperation: A study over multi-hop communications in wireless network
The imperfections of the propagation channel due to channel fading and noise from the front end receiver cause error in the received signal in communication systems. When network coding is applied, more errors occur because of error propagation due to the inexact decoding process. In this thesis we present a system called Partial Network Coding with Cooperation (PNC-COOP) for wireless ad hoc networks. It is a system which combines opportunistic network coding with decode-and-forward cooperative diversity technique in order to reduce this error propagation by trading off with some transmission degree of freedoms. PNC-COOP is a decentralized, energy efficient strategy which provides a substantial benefit over opportunistic network coding when transmission power is a concern. Using computer simulation, evaluated over a 3-hop communication scenario, 16-node wireless ad hoc network, it has been shown that PNC-COOP improves the BER performance by 5 dB compared to opportunistic network coding. On average, it reduces the energy used by each sender node around 9-10% and reduces the overall transmitted energy of the network by 3.5%. When retransmission is applied, PNC-COOP performs well at relatively low SNR. PNC-COOP provides less end-to-end delay than opportunistic network coding and direct transmission approach while the throughput and BER are comparable. The effectiveness of the scheme depends on the amount of network coding. Our simulation shows that PNC-COOP is applied to approximately 11-15% of the transmitted packets. Other important factors that affect the performance of the system are also described.

Joining Open Source Software Communities: An Analysis of Newbies' First Interactions on Project Mailing Lists
Open source software has become a powerful force in the world of computing. While once confined to the domain of technical specialists, people of all types have begun to adopt this software -- from the casual web-surfer who uses Firefox, to the professional web developer who codes in PHP or Python.

People interested in both seeking and receiving information related to an open source software project are often directed to its mailing lists. Therefore, many newcomers, or “newbies,” will have their first interactions with the project community there. These newbies are a sustaining force for open source software projects, making it worthwhile to investigate how these interactions play out and affect the newbies’ future participation.

To gain insight into the first experiences newbies have interacting with an open source software community, we conducted a study of eight mailing lists across four open source software projects: MediaWiki, GIMP, PostgreSQL, and Subversion. We analyzed the discussion threads initiated by newbies on those lists for information such as poster gender, nationality, politeness, helpfulness, and timeliness of response. Among the most interesting results, we found that newbies were generally treated very well, with nearly 80% receiving replies to their first post. We also found that receiving timely responses, especially within 48 hours of posting, had a positive correlation with that newbie continuing to participate on the mailing list over time. Somewhat surprisingly, we discovered that a newbie’s level of courtesy did not have a significant effect on whether or not that newbie received a reply.

A Multi-Bit Hybrid DSM over Full-Scale Range without Feedback DEM
Evolution of the mobile communication standards and proliferation of hand-held devices mandate stringent Analog-to-Digital Converter (ADC) specifications. Among various ADCs, a Delta-Sigma ADC is best known as a power-efficient ADC when more than 12b is required. However, a conventional discrete-time (DT) Delta-Sigma Modulator (DSM) is inadequate for low-power wideband applications due to the opamp settling requirement. Alternatively, a continuous-time (CT) DSM can be used to decrease power consumption but has its own disadvantages such as clock jitter sensitivity, RC time constant variation, and excess loop delay.

The wideband modulators are often implemented as single-loop high-order modulators in a deep submicron process. The high-order modulator typically has a quantizer overloading problem as the input signal approaches to a full-scale range. A pole-optimization method can be used to extend the linear input range but it inevitably decreases signal to quantization noise ratio. This causes power penalty since it limits the maximum input power available.

Another challenge is linearizing a nonlinear multi-bit Digital-to-Analog Converter (DAC). On one hand, the DAC can be linearized by element sizing, sorting, and calibration but these increase silicon area and power consumption. On the other hand, a Dynamic Element Matching algorithm (DEM) linearizes the DAC by averaging and shaping the mismatches with minimal design overhead. However, the DEM causes additional delay inside the feedback path. This can make the modulator unstable.

In this thesis, a multi-bit 3rd-order hybrid DSM with over full-scale range and no DEM in the critical feedback path is presented. Removing the DEM in the critical path enables minimizing latency in the feedback path. A digital feedforward structure allows processing the input signal over the full scale. Combined benefits of the CT/DT implementation help to reduce power consumption and to mitigate the loop delay. Measurement results from a prototype demonstrate the effectiveness of the proposed ideas.

Ultra Low Energy Digital Logic controller Design for Wireless Sensor Networks
Low energy design techniques for digital circuits are examined to determine their suitability for use in a digital logic controller for wireless sensor network nodes. Transistor level simulations are used to evaluate the techniques and those demonstrating an energy reduction are used to implement a digital logic controller. The digital controller for the wireless sensor node, fabricated in a 0.18μm CMOS process, operates at 350mV while consuming 336fJ per clock cycle with a 250kbps data rate. Lab measurements show a 98% reduction in energy consumption compared to an implementation that utilizes standard design techniques, making it the lowest energy digital controller for wireless sensor nodes to date.

An Ultra-Low Power Receiver for Wireless Sensor Networks
Ultra low-power transceiver design is a critical technology for wireless sensor networks. An ultra low-power super-regenerative receiver for BFSK signals has been designed and fabricated in a standard 0.18 um CMOS process. The use of BFSK allows the receiver to operate at higher data rates and also gives an SNR performance increase over the more traditional OOK modulation. At 1Mb/s the receiver consumes 0.4 nJ/b making it the lowest energy integrated super-regenerative receiver to date. Additional improvements to this receiver are also presented in order to further reduce the power consumption while also improving the sensitivity.

An Ultra-Low-Voltage High-Efficiency Transmitter for Wireless Sensor Networks
An ultra-low-voltage high-efficiency transmitter for wireless sensor networks is presented. It supports on-off keying and frequency-shift keying modulation schemes and integrates a fast frequency tuning feature to reduce energy waste during frequency setup period. The antenna is driven directly via a power oscillator to minimize overhead power loss from pre-driven circuits. A power oscillator design approach is established to achieve the highest efficiency possible with specific design constraints. The transmitter is designed in a 0.18-μm CMOS process and the frequency tuning time is as low as 72μs. With a 0.65-V supply, the transmitter can deliver up to 350μW radiated output power with the efficiency of 30% for the power oscillator and 26% for overall transmitter.

Type Correct Changes—A Safe Approach to Version Control Implementation
Ensuring correctness of real-world software applications is a challenging task. Testing can be used to find many bugs, but is typically not sufficient for proving correctness or even eliminating entire classes of bugs. However, formal proof and verification techniques tend to be very heavy weight and are simply not available for day to day use in many common programming environments.

We demonstrate a form of light-weight proof assistant by using the type checking features of the programming language Haskell with existing extensions. We apply this work to the Open Source version control system Darcs. The properties checked by our approach are derived directly from the data model used by Darcs. This allows us to eliminate entire classes of bugs at compile time. We also examine how these techniques improve the quality of the Darcs codebase and the challenges that arise when applying these techniques in practice.

Activity Recognition in Desktop Environments
Knowledge workers are struggling in the information flood. There is a growing interest in intelligent desktop environments that help knowledge workers organize their daily life. Intelligent desktop environments allow the desktop user to define a set of “activities” that characterize the user’s desktop work. These environments then attempt to identify the current activity of the user in order to provide various kinds of assistance. TaskTracer is one of these efforts. We classify activities into three levels: “task” as in TaskTracer, workflow, and operation. In this thesis, we concentrate on the two higher levels of activity – “task” and “workflow” -- and we present an activity recognition solution for each of them. To recognize tasks, we employ various supervised learning algorithms. The first approach is based on batch training, which has a heavy requirement for CPU time and memory. It is also insensitive to the user feedback, and it is likely to make repeated mistakes. To address these issues, we propose a novel online learning algorithm that is able to incorporate a richer set of features than our previous predictors. We prove an error bound for the algorithm and present experimental results that show improved accuracy and a 180-fold speedup on real user data. To recognize workflows, we first mine frequent workflow models from the TaskTracer event log. Discovering desktop workflows is difficult because they unfold over extended periods of time (days or weeks) and they are interleaved with many other workflows because of user multi-tasking. We describe an approach to discovering desktop workflows based on rich instrumentation of information flow actions such as copy/paste, SaveAs, file copy, attach file to email message, and save attachment. These actions allow us to construct a graph whose nodes are files, email messages, and web pages and whose edges are these information flow actions. A class of workflows that we call work procedures can be discovered by applying graph mining algorithms to find frequent subgraphs. After finding the workflow models, we create a Logical Hidden Markov Model (LHMM) for each mined model to represent the workflow in a form suitable for real-time recognition using the WARP relational inference algorithm.

Duty-cycle Controlled Switched Resistor Techniques for Tunable, Low-voltage Circuits
A duty-cycle controlled switched resistor is a tunable resistive element that uses pulse width modulation as the method of tuning. This presentation will describe the operation of switched resistors and propose several circuit architectures that are well suited to the use of switched resistors. These architectures include filters, mixers, and continuous time delta-sigma data converters. The duty-cycle controlled switched resistor is continuously tunable with low signal distortion and provides a tuning range that is independent of supply voltage. It consists of a single tunable element in the signal path and therefore does not suffer from the area and parasitic problems of digital element arrays. For these reasons, the duty-cycled controlled switched resistor is well suited to low-voltage systems that require PVT tuning and reconfigurability.

Network Coding Techniques for Downlink Beamforming-SDMA Channels
As the demand for bandwidth grows, many wireless communication systems now employ Multiple-Input/Multiple-Output (MIMO) techniques to improve throughput. Thus, we propose a joint optimization of Network Coding (NC) and MIMO techniques to improve the downlink channel throughput of a cellular base station. Specifically, we consider a MIMO base station with multiple transmit antennas that serves multiple users simultaneously by generating multiple signal beams with well-defined beamforming weight vectors where each beam intends for a particular user. Given a large number of users and a small number of transmit antennas, a base station must decide, at any transmission opportunity, which group of users it should transmit packets to, in order to maximize the overall throughput. To that end, we propose a method for grouping users that takes advantages of NC technique and the orthogonality of user channels to improve the overall throughput. Our simulation results indicate that the proposed method can achieve higher throughput over the existing techniques, especially in highly lossy environments.

Image Features and Learning Algorithms for Biological, Generic and Social Object Recognition
Automated recognition of object categories in images is a critical step for many real-world computer vision applications. Interest region detectors and region descriptors have been widely employed to tackle the variability of objects in pose, scale, lighting, texture, color, and so on. Different types of object recognition problems usually require different image features and corresponding learning algorithms. This dissertation focuses on the design, evaluation and application of new image features and learning algorithms for the recognition of biological, generic and social objects. The first part of the dissertation introduces a new structure-based interest region detector called the principal curvature-based region detector (PCBR) which detects stable watershed regions that are robust to local intensity perturbations. This detector is specifically designed for region detection for biological objects. Several recognition architectures are then developed that fuse visual information from disparate types of image features for the categorization of complex objects. The described image features and learning algorithms achieve excellent performance on the difficult stonefly larvae dataset. The second part of the dissertation presents studies of methods for visual codebook learning and their application to object recognition. The dissertation first introduces the methodology and application of generative visual codebooks for stonefly recognition and introduces a discriminative evaluation methodology based on a maximum mutual information criterion. Then a new generative/discriminative visual codebook learning algorithm, called iterative discriminative clustering (IDC), is presented that refines the centers and the shapes of the generative codewords for improved discriminative power. It is followed by a novel codebook learning algorithm that builds multiple codebooks that are non-redundant in discriminative power. All these visual codebook learning algorithms achieve high performance on both biological and generic object recognition tasks. The final part of the dissertation describes a socially-driven clothes recognition system for an intelligent fitting-room system. The dissertation presents the results of a user study to identify the key factors for clothes recognition. It then describes learning algorithms for recognizing these key factors from clothes images using various image features. The clothes recognition system successfully enables automated social fashion information retrieval for an enhanced clothes shopping experience.

Hierarchical Structure Discovery in Reinforcement Learning
Reinforcement Learning within a Markov Decision Process (MDP), the principal theoretical formalism for sequential decision-making in stochastic environments, is inefficient due to the combinatorial explosion of the state and action spaces. Hierarchical Reinforcement Learning (HRL) leverages hierarchical structure within the MDP, in the spirit of the divide-and-conquer strategy, to help curb this inefficiency. However, the biggest detraction of most state-of-the-art HRL systems is that an external domain expert with prior knowledge of the MDP being solved must supply this structural information to the agent. While the HRL community has made isolated attempts to address this shortcoming, this proposal outlines a holistic research agenda for the autonomous discovery of hierarchical structure in MDPs, including the development of a rigorous theoretical foundation for the characterization of hierarchical structure, the design of algorithms for the discovery of hierarchical structure from actions models and demonstrations, and the transfer of hierarchical structure to new unknown MDPs in order to expedite their solutions.

Modeling and Analysis of Output Spectrum of Digital-to-Time Conversion Based Frequency Synthesizers
Frequency synthesizers are critical components of all communication systems. Digital-to-time conversion based frequency synthesis architecture is a relatively recent architecture with some promising unique characteristics. It is capable of generating wide range of frequencies with very low switching times. It is also uniquely conducive to integration on an IC. The DTC architecture, however, also presents its own unique set of analysis challenges. The seemingly unpredictable set of frequency domain spurious tones is one such important problem. A theoretical framework is established for the modeling and analysis of digital-to-time based frequency synthesizers. Some preliminary results about its static spur spectrum are presented. The proposed PhD research will systematically model and analyze static and dynamic spectra. Better understanding of undesirable frequency content can lead to methods to mitigate undesirable aspects of the output spectrum. The use of DTC in transmitter architectures based on pulse width modulation (PWM) methods will be explored.

Network Coding for Media Storage and Streaming over the Internet
Recent years have witnessed an explosive growth in multimedia streaming applications over the Internet. However, current media streaming and storage systems based on client-server model like YouTube do not scale well in terms of bandwidth and computation. This work describes a distributed, scalable Peer-to-Peer system for Media Storage and Streaming over the Internet using Network Coding (PMES2). The proposed system aims to increase the media streaming throughput and data resiliency against peer departures and failures using peer diversity. First, we present a network coding scheme that codes and disperses data in such a way to provide robust performance against peer departures and failures for a given data redundancy level. Second, to maintain a sufficient level of data redundancy in the system, we propose and describe a data replenishment process using random network coding to counter the data deletion due to peer departures and failures. The proposed data replenishment is designed to be distributed, scalable, and does not require the presence of the original data. Peers take part in the data replenishment process in a random and independent manner, yet collectively, data in the network is robust against peer departures and failures. Third, we introduce a path-diversity protocol for a client to simultaneously stream a video from multiple peers with minimal delay and throughput fluctuation. Simulations demonstrate that under certain scenarios, our proposed scheme can result in bandwidth saving up to 60% over the traditional scheme.

High-Speed Low-Complexity VLSI Architecture Design for Channel Codes
In this work, efficient VLSI architectures are explored for a 4-dimensional, 8 phase-shift keying, trellis coded modulation (4-D 8PSK TCM) decoder. First, a low-complexity architecture for transition metrics unit (TMU) is proposed based on substructure sharing, which significantly reduces the required computation without degrading the performance. Then, a power efficient scheme by applying T-algorithm on branch metrics (BMs) is proposed for Viterbi decoder (VD). Unlike the previous works which usually apply T-algorithm on path metrics (PMs), thus heavily increasing the critical path, the new scheme does not affect the clock speed of the decoder. Furthermore, a hybrid T-algorithm for VD is developed by applying T-algorithm on both BMs and PMs, which reduces computations by as much as 50% from the conventional T-algorithm applied on PMs. When T-algorithm is implemented on PMs, the “searching-for-the-optimal-metric” operation will slow down the clock speed. Although there have been a few schemes proposed to overcome the problem by using the estimated optimal metric, instead of searching for the accurate one each cycle, they will cause significant bit-error-rate (BER) performance loss for the 4-D 8PSK TCM system. To maintain a high speed as well as a good BER performance for T-algorithm on PMs, a pre-computation architecture is proposed with no performance loss and negligible computation overhead. Our future works include design for survive memory unit in VD, architecture design for pragmatic TCM decoder in WiMAX and study of the soft decoding algorithm for punctured convolutional codes.

Revisiting Output Coding for Sequential Supervised Learning
Markov models are commonly used for joint inference of label sequences. Unfortunately, inference scales quadratically in the number of labels, which is problematic for training methods where inference is repeatedly preformed and is the primary computational bottleneck for large label sets. Recent work has used output coding to address this issue by converting a problem with many labels to a set of problems with binary labels. Models were independently trained for each binary problem, at a much reduced computational cost, and then combined for joint inference over the original labels. Here we revisit this idea and show through experiments on synthetic and benchmark data sets that the approach can perform poorly when it is critical to explicitly capture the Markovian transition structure of the large-label problem. We then describe a simple cascade-training approach and show that it can improve performance on such problems with negligible computational overhead.

UCT for Tactical Assault Battles in Real-Time Strategy Games
We consider the problem of tactical assault planning in real-time strategy games where a team of friendly agents must launch an assault on an enemy. This problem offers many challenges including a highly dynamic and uncertain environment, multiple agents, durative actions, numeric attributes, and different optimization objectives. While the dynamics of this problem are quite complex, it is often possible to provide or learn a coarse simulation-based model of a tactical domain, which makes Monte-Carlo planning an attractive approach. In this thesis, we investigate the use of UCT, a recent Monte-Carlo planning algorithm for this problem. UCT has recently shown impressive successes in the area of games, particularly Go, but has not yet been considered in the context of multi-agent tactical planning. We discuss the challenges of adapting UCT to our domain and an implementation which allows for the optimization of user specified objective functions. We present an evaluation of our approach on a range of tactical assault problems with different objectives in the RTS game Wargus. The results indicate that our planner is able to generate superior plans compared to several baselines and a human player.

Behavior Graphs for Data-driven Animation of 3-D Characters
In this paper, we present a user-in-the-loop method for the design of an interactive motion data structure that benefits from the advantages of both motion graphs and blend-based techniques. Our novel approach automatically analyzes a traditional motion graph built from labeled motion clips. The result is a more condensed, coarser graph which we call the Behavior Finite State Machine (BFSM). Each node of the BFSM represents a single behavior that may be continuously parameterized. An edge in the BFSM represents a valid transition between two behaviors, with the transition probability indicating the likelihood of such a transition. Our focus is on user-centered, semi-automatic methods for aiding in the construction and fine-tuning of such machines. Since the transitions and parameterized behavior spaces are based on constructing time-warps between motion clips, we present an intuitive process that allows the user to construct these data structures necessary for BFSM design. We present the results of our approach using two dynamic interactive examples, locomotion and martial arts. We demonstrate the use of the BFSM to generate controllable motion in real-time, use the BFSM for offline motion synthesis using A* search, and we generate autonomous character navigation with obstacle avoidance in a virtual environment, and discuss the strengths and weaknesses of our approach.

Automated Mask Generation for Controllable Parametrized Blending
Blending and masking are common animation techniques that are often used together to increase the range of motions or actions that a character can perform. A commonly employed tactic is to blend animations with the currently playing motion, localized to a portion of the character's body. This has traditionally been accomplished by using manually determined masks to blend the respective animations with the motion currently being played. This is cumbersome as each mask needs to be manually determined by an animator or programmer having special expertise, while also consuming valuable time.

We provide a solution for certain scenarios for which our algorithm can compute the mask automatically. We introduce a method to compute what we call the joint importance measure, to determine the degree by which each joint of the character affects a difference motion compared to a baseline motion. We then use the magnitude of this joint importance to determine the mask, which is used to combine the motions and synthesize the final blended and parametrized animation.

Low-Power Dynamic CMOS Circuits in High-performance Memory Arrays
Dynamic CMOS circuits are commonly used in high-performance memory arrays to implement wide-NOR logic functions for their read and search operations. This is because dynamic circuits have significantly higher speed and lower area compared to static circuits for such structures. Register File (RF) arrays are located at the top of memory hierarchy of microprocessors providing the fastest data access. Reading data from RF arrays involves selection of data from memory cells based on input addresses which is equivalent to the logical operation performed by wide-NOR gates. Content Addressable Memory (CAM) arrays are essential for high-performance comparison of an input data against a set of stored data. The hit or miss information from each memory cell is combined in wide-NOR gate like structures to generate the final miss or match information of the whole input search string.

The advantages of higher performance and lower area of dynamic circuits come at a cost of higher power and lower noise robustness compared to static circuits. With the advancement of process technology scaling, there is a trend of increase in leakage current which impacts both the power consumption and noise immunity. This dissertation presents design approaches to improve power consumption of high-performance RF and CAM arrays while maintaining their noise immunity.

The characteristics of an RF array depend on its bit-line organization. This dissertation investigates few options of arranging the bit-lines with the same noise robustness and their impact on power and performance. The read evaluation circuits of traditional RF arrays are implemented with NMOS-device based domino gates where NMOS devices are used for pulling down the dynamic nodes. An RF array with PMOS-device based domino gates is proposed, where the read evaluation is performed with PMOS devices instead of NMOS devices.

To improve power of RF based CAM arrays, an 11-transitor CAM cell is proposed. Its read/write operations are independent of the stored and/or search data and cell stability is not dependent on its read operation. A low-power Ternary Content Addressable Memory (TCAM) array using 16-transistor core memory cells is presented for network applications. It uses same bitlines for both read and search operations.

Low Power Design Techniques for High Speed Pipelined ADCs
Real world is analog but the processing of signals can best be done in digital domain. So the need for Analog to Digital Converters (ADCs) is ever rising as more and more applications set in. With the advent of mobile technology, power in electronic equipment is being driven down to get more battery life. Because of their ubiquitous nature, ADCs are prime blocks in the signal chain in which power is intended to be reduced. In this thesis, four techniques to reduce power in high speed pipelined ADCs have been proposed. The first is the capacitor and opamp Sharing Technique that reduces load on the first stage opamp by three fold. The second is the capacitor reset technique that aids removing the sample and hold block to reduce power. The third is a modified MDAC which can take rail to rail input swing to get an extra bit out thus getting rid of a power hungry opamp. The fourth is the hybrid architecture which makes use of an asynchronous SAR ADC as the backend of a pipelined ADC to save power. Measurement and simulation results that prove the efficiency of the proposed techniques are presented.

Applying Machine Learning on Prediction, Recommendation and integration
The explosion of the electronic information has introduced a big challenge for computer scientists to invent smart and efficient ways of finding information and improving the user experience. Machine learning, on the other hand, has been an active research area for decades. Recently, there is a growing interest in applying machine learning technologies to help computer users find information and better organize electronic resources. This thesis will explore this idea in three applications: the TaskTracer FolderPredictor, Stacking Recommendation Engines, and Integrating Learning and Reasoning through Markov Logic.

Rare Category Detection Using Hierarchical Mean Shift
Many applications in surveillance, monitoring, scientific discovery, and data cleaning require the identification of anomalies. Although many methods have been developed to identify statistically significant anomalies, a more difficult task is to identify anomalies that are both interesting and statistically significant. Rare category detection is an emerging area of machine learning that has been proposed to address this problem using a "human-in-the-loop" approach. The goal of a rare category detection algorithm is to present the user with data points that are considered by the algorithm to be meaningful anomalies such that the user ultimately encounters a rare category of interest in as few queries as possible.

We present a new approach to rare category detection using a hierarchical mean shift procedure. In our approach, a hierarchy is created by repeatedly applying mean shift with increasing bandwidth on the entire data set. This hierarchy allows us to identify anomalies in the data set at different scales, which are then posed as queries to the user. The main advantage of this methodology over existing approaches is that it does not require any knowledge of the dataset such as the total number of classes or the prior probabilities of the classes. Results on real-world data sets show that our hierarchical mean shift approach performs consistently better than previous techniques.

Structured Network Coding
Network coding is a transmission paradigm that is known to achieve better network throughput in certain multicast topologies; however, the practicality of network coding has been questioned due to its high computational complexity. One of the drawbacks of using network coding is the long decoding times, this is mainly due to the time spent solving the linear equations in order decode the original blocks. Clearly, a more efficient way is mandatory for network coding to be practical for large files. We propose a new scheme called structured network coding where in we restricts the size of the universe of allowable encodings. This we believe is going to reduce the decoding time that has been major problem with other network coding schemes.

In this project we study this new approach. We show how this approach would reduce the decoding complexity and evaluate its performance using a wireless mesh simulator.

An Ultra Low-Power Frequency Reference for Timekeeping Applications
An ultra low power crystal oscillator that provides a frequency reference for battery powered timekeeping applications is presented. An amplitude control circuit is employed to ensure that minimum current is consumed. A subthreshold voltage regulator provides a supply voltage for the oscillator with minimum current consumption. The oscillator and regulator are designed in a standard 0.18μm CMOS process. Measured results show the regulator works for battery voltages that range from 1.4 - 4.5V. The crystal oscillator consumes a current of 17.6nA at a minimum supply voltage of 0.8V, making it the lowest power crystal oscillator demonstrated to date. The complete system (oscillator and regulator) consumes a current of 30.6nA when a battery voltage of 3.3V is used.

A Nano-Power Wake-Up Circuit for RF Harvesting Wireless Sensor Networks
A fully integrated CMOS latched comparator is presented for use as a wake-up circuit that is attached to an RF energy harvester in a battery free wireless sensor network. The system consumes less than 50nA static current at 20°C and dissipates 300fJ of energy per conversion. The comparator comprises of a series of level-shifting leakage-mode inverters. Its latching behavior is obtained by supplying the power to each stage from the inverted output of the last stage via a resistor-string voltage divider. This 60nW circuit is the solution with the lowest static power consumption proposed to date for synchronizing nodes in a sensor network.

Modeling the Graphical and Physical Properties of Sand
Simulating geographic terrain environments typically involves using a digital elevation map (DEM) to produce polygonal graphics objects that can be visualized with a computer. These graphical objects are built by sampling a DEM and then translating grid vertices to correspond to the terrain's height. Many of these digital elevation maps are captured by satellite with resolution usually around 10 to 100m per pixel. This works well for most graphical applications but suffers from a loss of terrain detail when visualizing the surface at ground level. For research at the Jet Propulsion Laboratory (JPL), which simulates vehicles such as rovers on planetary bodies, it is important that additional terrain details such as sand granularity and density are represented as features of the terrain. Planetary bodies such as Mars exhibit very fine particles of sand that could inhibit a rover from a successful exploration mission.

Unfortunately, this simulated terrain environment is unable to account for how a rover interacts with sand, mostly due to its computationally complex nature. However, recent computer graphics advances and research allow for this to become a reality. In particular, graphics processing units (GPUs) on modern graphics hardware has advanced to produce stunning graphics visualizations while maintaining real-time simulation interaction. A new software development kit called CUDA ("Compute Unified Device Architecture") has been developed by NVIDIA as a means to harness the power of a GPU. In fact, CUDA is designed to be highly parallelizable so that many computations occur simultaneously. Specifically in regard to visualizing and modeling sand behavior, this is useful in computing thousands of collisions of individual particles of sand in real-time. The use of sand simulation through CUDA to a terrain simulation environment will add to the simulation's robustness. Thus, this research will explore and implement a virtual sand particle simulation for use in virtual terrain environments, such as used by researchers at JPL.

An Enhanced Swing Differential Colpitts CMOS VCO for Low-Voltage Operations
A voltage-controlled oscillator (VCO) with digital amplitude control is designed in a 1P8M 0.13 µm CMOS process. The proposed enhanced swing differential Colpitts VCO (ESDC-VCO) dramatically improves the swing of a Colpitts VCO by allowing the signal to go below ground as well above the supply voltage. Start-up gain improves by more than 50% compared the traditional Colpitts VCO. The ESDC-VCO operates at 4.9GHz with a 0.475-V supply and consumes 2.7mW with a measured phase noise of -136.2 dBc/Hz at 3-MHz frequency offset. The ESDC-VCO achieves a figure of merit (FOM) of 196.2 dBc/Hz, making it the highest performing integrated LC oscillator to date.

Some Communication Algorithms for Gaussian and Eisenstein Networks
Interconnection networks play an important role in designing high performance computers. Recently two new classes of interconnection networks based on the concept of Gaussian and Eisenstein integers are introduced. In this research, our plan is to develop efficient routing and broadcasting algorithms for these networks. Furthermore, fault tolerant algorithms in the presence of node and link failures are also investigated. Some resource placement methods for these networks are also studied.

Classification of Motion Capture Sequences
Motion capture data is a digital representation of the complex temporal structure of human motion. Motion capture is widely used for data-driven animation in sports, medicine and entertainment, because of its ability to capture complex and realistic motions. Due to its efficiency and cost, methods for reusing collections of motion capture data are becoming important in the field of computer animation. These motions can then be used for motion blending and morphing, which in turn requires identification and retrieval of the motion from the large collection of motions. Currently, motion data is manually labeled and segmented through a labor-intensive process. This thesis investigates algorithms for the classification of motion capture sequences. This classification task is challenging due to the data being high dimensional, continuous, and time-variant. The main contribution of this thesis is an empirical comparison of a variety of classification algorithms for motion capture sequences. We investigate three different aspects of these classification algorithms: 1) the use of discrete versus continuous models of the data, 2) generative versus discriminative models and 3) dimensionality reduction through Principal Component Analysis, a linear technique, versus the Gaussian Process Latent Variable Model, a non-linear technique.

Zinc Tin Oxide Thin-Film Transistor Circuits
The primary objective of this thesis is to develop a process for fabricating integrated circuits based on thin-film transistors (TFTs) using zinc tin oxide (ZTO) as the channel layer. ZTO, in contrast to indium- or gallium-based amorphous oxide semiconductors (AOS), is perceived to be a more commercially viable AOS choice due to its low cost and ability to be deposited via DC reactive sputtering. In the absence of an acceptable ZTO wet etch process, a plasma-etching process using Ar/CH4 is developed for both 1:1 and 2:1 ZTO compositions. An Ar/CH4 plasma etch process is also designed for indium gallium oxide (IGO), indium gallium zinc oxide (IGZO), and indium tin oxide (ITO). Ar/CH4 dry etches have excellent selectivity with respect to SiO2, providing a route for obtaining patterned ZTO channels. A critical asset of ZTO process integration involves removing polymer deposits after ZTO etching without active layer damage.

A ZTO process is developed for the fabrication of integrated circuits which use ZTO channel enhancement-mode TFTs. Such ZTO TFTs exhibit incremental and average mobilities of 23 and 18 mobility, respectively, turn-on voltages around 0 to 1.5 V and subthreshold swings below 0.5 V/dec when annealed in air at 400°C for 1 hour. Several types of ZTO TFT circuits are realized for the first time. Despite large parasitic capacitances due to large gate-source and gate-drain overlaps, AC/DC rectifiers are fabricated and found to operate in the MHz range. Thus, they are usable for RFID and other equivalent speed applications. Finally, a ZTO process for simultaneously fabricating both enhancement-mode and depletion-mode TFTs on a single substrate using a single target and anneal step is developed. This dual-channel process is used to build a high-gain two-transistor enhancement/depletion inverter. At a rail voltage of 10 V, this inverter has a gain of 10.6 V/V, the highest yet reported for an AOS-based inverter. This E/D inverter is an important new functional block which will enable the realization of more complex digital logic circuits.

Video Streaming in Unstructured p2p Networks
With the increase in demand for streaming media capabilities across the Internet, the focus has shifted from traditional client-server to peer-to-peer approaches. Content Distribution Networks (CDNs) have also recently moved from web acceleration to media streaming. P2P CDNs can be used both as a delivery mechanism and as an independent network. However, media streaming poses different challenges from traditional content distribution, such as in-order distribution; and p2p networks use more traffic, and lack QoS control and measurement. In addition, constraints like a high churn rate and small upload bandwidths can affect the video playback at the peers. We find that certain strategies can be used to optimize the streaming experience at the receiving nodes, while also being scalable and robust to churn. This project presents the experimental results of MPEG-4 video streaming using different approaches in unstructured p2p networks.

Correlated Level Shifting as a Power-Saving Method to Reduce the Effects of Finite DC Gain and Signal Swing in Opamps
This thesis presents methods to reduce the effects of finite opamp DC gain, output voltage swing limitations in opamps, and component mismatches. The primary contribution of this thesis is a new switched capacitor method named correlated level shifting (CLS). CLS enables true rail-to-rail operation by storing an estimate of the desired signal on a capacitor during an “estimate” phase, and subtracting the signal from the active circuitry (nominally an opamp) during a “level shift” phase. This is done within the confines of a feedback loop. Subtracting the signal returns the opamp output to its preferred operating point which reduces the error even if the error-free output signal is larger than the supply. The effective loop-gain is the product of the loop-gains during the estimate and level shift phases. This enables, for example, a two-stage opamp to have the accuracy of a four-stage opamp. It also enables full utilization of the power supply since the gain block’s output voltage can exceed the power supply. This high accuracy operation to and beyond the rail is unprecedented. The thesis shows that the full utilization of the power supply and the increased DC effective loop gain leads to a significant savings in power compared to existing techniques.

The methods are presented in the context of pipelined analog-to-digital converters; although the methods can be used with other circuits that use opamps or are sensitive to component mismatch. An overview of the detrimental effects of reduced signal swing and low DC gain is given with an emphasis on the cost in power to correct these deficiencies when limited to existing circuit techniques. CLS is then shown to correct these deficiencies without increasing power. A detailed explanation of CLS operation is given, as are measured results from a 12-bit pipelined analog-to-digital converter that was fabricated using a 0.18μ CMOS process. The results included better than 10-bit performance with true rail-to-rail operation.

An overview of calibration is also given and the limitations are discussed. An argument is made that using CLS in addition to calibration will reduce power by increasing signal-to-noise ratio and reducing and linearizing the errors due to finite opamp gain. In addition, a method to reduce the effects of mismatch by measuring the relative size of elements is presented.

Finally, several avenues for future research into CLS are given.

Continuous Time Input Pipeline ADCs
Analog-to-digital converters (ADCs) convert analog continuous time signals into discrete time, digital format. One precondition that must be met for conventional nyquist rate ADCs is that the input signal must be suitably band-limited to an input bandwidth less than the nyquist frequency. This mandates expensive anti-alias filters which contribute to system noise and distortion degradation. By choosing an OSR of 2 and adopting simple linear phase filtering techniques, significant inherent anti-alias filtering is achieved, avoiding the need for an explicit anti-alias filter in many applications. Additionally the proposed continuous time input pipeline ADC eases a number of other challenges present in conventional switched capacitor ADCs:- sampled opamp noise folding, sampling distortion, ADC area, switched-capacitor pipeline ADC input loading.

Performance Evaluation of Some Classes of Balanced Codes
In a balanced code each codeword contains equal number of 1's and 0's. In this project the power spectrum densities of two classes of balanced codes are evaluated.

Myopic Policies for Budgeted Optimization with Constrained Experiments
Motivated by a real-world problem, we study a novel setting for budgeted optimization where the goal is to optimize an unknown function f(x) given a budget. In our setting, it is not practical to request samples of f(x) at precise input values due to the formidable cost of experimental setup at precise values. Rather, we may request constrained experiments, which give the experimenter constraints on x for which they must return f(x). Importantly, as the constraints become looser, the experimental cost decreases, but the uncertainty about the location of the next observation increases. Our problem is to manage this trade-off by selecting a sequence of constrained experiments to best optimize f within the budget. We propose a number of myopic policies for selecting constrained experiments using both model-free and model-based approaches, inspired by policies for unconstrained settings. Experiments on synthetic and real-world functions indicate that our policies outperform random selection, that the model-based policies are superior to model-free ones, and give insights into which policies are preferable overall.

PHP Cloud Computing Platform
Most data-mining organizations and research groups have very large amounts of data – usually in giga-, tera- or peta-bytes – that need to be processed in different ways. In essence it is usually the same data that goes through different applications to produce different reports.

Considering the size of these copious amounts of data, finding an efficient way of distributing these computable applications or tasks on a massively-parallel processing system is becoming important. One such software framework was introduced by Google - named MapReduce.

But the design makes the system highly coupled with the framework. An implementation of a new framework based on the original intentions is presented which also automatically parallelizes the map tasks, but with much less coupling between the modules. To show case the simplicity of the framework, I have implemented an example map/reduce application on a prototype of this framework.

Visualization and Design Systems for Road Infrastructure
Transportation infrastructure provides a vital service for the functionality of a city. The efficient design of road networks poses an interesting topic in computer science for digital content developers. For civil engineers, the visualization of analysis results on infrastructure both efficiently and intuitively is crucial. The following contributions are made to these areas:

• Street Network Design - A system built around tensor field design is proposed. Necessary background information is discussed and a set of tools are developed. Generated street networks are shown to demonstrate the effectiveness of the system.
• Bridge Analysis Visualization - A unique system to visualize the analysis results of bridges is discussed. Methods used to procedural model a bridge and visualize analytical information over the generated model in an intuitive manner are detailed.

An Implementation of Graph Cut Textures: Image and Video Synthesis Using Graph Cuts
It describes a new algorithm for image and video texture synthesis. In this approach, patch regions from a sample image or video are transformed and copied to the output and then stitched together along optimal seams to generate a new (and typically larger) output. In contrast to other techniques, the size of the patch is not chosen a-priori, but instead a graph cut technique is used to determine the optimal patch region for any given offset between the input and output texture. Unlike dynamic programming, the graph cut technique for seam optimization is applicable in any dimension. It specifically explores it in 2D and 3D to perform video texture synthesis in addition to regular image synthesis. It presents approximative offset search techniques that work well in conjunction with the presented patch size optimization. It shows results for synthesizing regular, random, and natural images and videos. It also demonstrates how this method can be used to interactively merge different images to generate new scenes.

Creating and Editing Motion Machines for 3D Characters
Recent efforts in user-control of data-driven characters have focused on designing high-level graph data-structures that we call a Behavior Finite State Machine (BFSM). A BFSM is an interactive data-structure that benefits from the advantages of both motion graphs and blend-based techniques for generating animated motion. Each node in a BFSM represents a single behavior that can be parametrized. Each edge represents a valid transition between two behaviors and is associated with a probability that indicates the likelihood of the transition. This work focuses on "semi-automatic" and "user-in-the-loop" techniques for creating and editing a BFSM. We present a "mining" approach to learn the structure of a BFSM from a set of annotated motion-clips. We also present several optimization-based approaches to edit the BFSM and we evaluate them with a comparative study.

q-ary, limited magnitude error control codes
Error control coding have become a crucial part of communication and computer systems due to their effectiveness in achieving reliable transmission and storage. In the proposed thesis, we consider codes over the alphabet Zq = {0, 1, ..., q-1} correcting/detecting errors of limited magnitude l. That is, the channel is such that when a symbol s is transmitted, the corresponding received symbol, say s', may suffer an error of maximum magnitude l: s - l ≤ s' ≤ s + l.

An interesting application for such channel is the multi-level flash memory. Multi-level flash achieves higher storage capacity by programming the cells into one of q possible threshold levels. Errors in this case typically change a cell’s value into an adjacent threshold level. Thus, we can assume that the maximum error magnitude is known.

As the notion of limited magnitude errors is a recent one, the main goal of the proposed thesis is to determine how, if at all, this piece of information (i.e. knowing the maximum error magnitude) helps designing more efficient codes, i.e. ones that use less redundancy yet keep the same error detecting/correcting capabilities. Error control codes for the underlined channel are proposed. Moreover, open questions for further research are given.

A Low Voltage Micropower GPS Receiver RF Front-End
A fully integrated CMOS GPS receiver RF front end optimized for low power operation is presented. The system is designed for low voltage applications, operating with a supply voltage as low as 250 mV. A new low voltage LNA offering wideband input matching, high gain, and excellent reverse isolation is discussed. In addition, a low voltage quadrature oscillator with immunity to changes in the power supply voltage and excellent phase noise performance is presented. To complete the system, a low voltage mixer is developed with optimized switches, giving the best possible performance at very low power levels. A prototype has been fabricated in a 0.13um CMOS process. The prototype exhibits a gain of 42 dB, a noise figure of 8.6 dB, and an oscillator phase noise of -113.8 dBc/Hz at a 1 MHz offset while consuming a maximum of 580 uW of power and requiring no external components.

Improvements of Timing Accuracy for Multi-Gigahertz Track/Hold Circuits
Multi-Gigahertz sampling rate, 5-8 bits Analog-to-Digital Converters (ADC) are used in many signal communication and processing applications, such as UWB system, SerDes receivers, and software-radio system for digital TVs. In order to meet the stringent performance requirement of such ADCs, the T/H circuit should be with high linearity and wide bandwidth. Unfortunately, the performance of the ADC is also limited by the timing accuracy of the sampling clock, even small sampling uncertainty can introduce large error in sampled voltage and result in harmonic distortions at the output. For different architecture of the T/H circuit, the timing error can be from the clock random jitter or the phase skew among multi-phase clocks.

For the ADC with global T/H circuit in front-end, an architecture with sine-wave clock will be introduced for less random clock jitter. First, the signal-dependent sampling error will be analyzed mathematically, and the comparison of the calculation results and simulation results will be presented. Secondly, from the SFDR simulation of high speed NMOS T/H circuit with different kind of sampling clock, we can compare the effects of the signal-dependent nonlinearity and other non-ideal effects to the SFDR of high speed T/H. Based on the above analysis, a new architecture for multi-gigahertz sampling rate ADC will be introduced.

For the ADC with time-interleaved T/Hs, a new method to detect and calibrate the static timing error among the multi-channels will be introduced. First, different timing error sources in high speed time-interleaved T/H will be analyzed. Secondly, a histogram based timing error detector will be proposed, it will include not only the skew in the multi-phase clocks, but also the mismatch among the multi-channel T/H circuits. An 8-channel 10GS/s T/H with timing error calibration circuits have been implemented with IBM 90nm CMOS process, the static timing error before and after timing calibration will be presented from the measurement results.

Wideband High-Resolution 3rd Order Hybrid Delta-Sigma Modulator in 65nm CMOS
A recent mobile communication standard, Wireless Broadband, offers several benefits compared with other standards. One of the benefits is a high data rate even when a subscriber travels around 70miles/hour. The standard, however, demands challenging Analog-to-Digital Converter (ADC) design requirements: wide bandwidth (BW>9MHz) and high data rate (>100Mbps), while maintaining power consumption as low as possible.

Among various ADCs, a delta-sigma ADC is known as a power-efficient ADC when high resolution (>12b) is required. A conventional discrete-time (DT) Delta-Sigma Modulator (DSM), however, is inadequate for the low-power wideband application due to the opamp settling requirement. As an alternative, a continuous-time (CT) DSM can be used to decrease power consumption but has its own disadvantages such as clock jitter and instability.

To overcome the shortcomings of DT and CT implementation, a 4-bit 3rd-order hybrid DSM is presented. The first two CT integrators minimize power consumption and the last DT integrator eliminates the finite loop delay. The dynamic element matching algorithm in the critical path for the multi-bit Digital-to-Analog Converter (DAC) is removed to speed up the feedback operation between the quantizer and DAC. Furthermore, the modulator uses the switched-R-MOSFET-C tuning scheme to mitigate the DAC clock jitter, time constant variation, and finite opamp delay. Detailed system/circuit implementation issues are provided along with simulation results.

Manufacture and Characterization of Materials and Devices for Thin-film Transistors
A class of inorganic thin-film transistor (TFT) semiconductor materials has emerged involving oxides composed of post-transitional cations. This thesis is devoted to the pursuit of topics involving the development of these materials for TFT applications: Deposition of zinc oxide and zinc tin oxide semiconductor layers via reactive sputtering from a metal target, and the characterization of indium gallium zinc oxide (IGZO)-based TFTs utilizing various insulator materials as the gate dielectric.

The first topic involves the deposition of oxide semiconductor layers via reactive sputtering from a metal target. Reactive sputtering using a metallic target has several advantages compared to deposition methods in which a ceramic target is used. Reactive sputtering using a metallic target results in a higher deposition rate. The physical properties of the metal lead to a more durable target of higher purity and superior thermal conductivity. Finally, a metallic target is easier to fabricate, requiring less care and cost than is involved in the fabrication of a ceramic target. In this thesis two oxide semiconductors are fabricated utilizing reactive sputtering from a metal target: zinc oxide and zinc tin oxide. With optimized processing parameters, zinc oxide and zinc tin oxide via this deposition method exhibit similar characteristics to TFTs fabricated via sputtering from a ceramic target.

Additionally the effects of gate capacitance density and gate dielectric material are explored utilizing TFTs with IGZO as the semiconductor layers. IGZO-based TFTs exhibit ideal behavior with improved TFT performance such as higher current drive at a given overvoltage, a decrease in the subthreshold swing, and a decrease in the magnitude of the turn-on voltage. Additionally it is shown that silicon dioxide is the preferred dielectric material, with silicon nitride a poor choice for oxide-based TFTs.

Finally a simple method to characterize the band tail state distribution near the conduction band minimum of a semiconductor by analyzing two-terminal current-voltage characteristics of a TFT with a floating gate is presented. The characteristics trap energy (ET) as a function of post-deposition annealing temperature is shown to correlate very well with IGZO TFT performance, with a lower value of ET, corresponding to a more abrupt distribution of band tail states, correlating with improved TFT mobility.

Stability and Temperature-Dependence Assessment of IGZO TFTs
Amorphous oxide semiconductors (AOSs) are of great current interest for thin-film transistor (TFT) channel layer applications. In particular, indium gallium zinc oxide (IGZO) is under intense development for commercial applications because of its demonstrated high performance at low processing temperatures. The objective of the research presented in this thesis is to provide detailed assessments of device stability, temperature dependence, and related phenomena for IGZO-based TFTs processed at temperatures between 200°C and 300°C. TFTs tested exhibit an almost rigid shift in log10(ID) – VGS transfer curves in which the turn-on voltage, VON, moves to a more positive gate voltage with increasing stress time during constant-voltage bias-stress testing of IGZO TFTs. TFT stability is improved as the post-deposition annealing temperature increases over the temperature range of 200 – 300°C. The turn-on voltage shift induced by constant-voltage bias-stressing is at least partially reversible; VON tends to recover towards its initial value of VON if the TFT is left unbiased in the dark for a prolonged period of time and better recovery is observed for a longer recovery period. VON for a TFT can be set equal to zero after bias-stress testing if the TFT electrodes are grounded and the TFT is maintained in the dark for a prolonged period of time. Attempts to accelerate the recovery process by application of a negative gate bias at elevated temperature (i.e., 100°C) were unsuccessful, resulting in severely degraded subthreshold swing. An almost rigid log10(ID) –VGS transfer curve shift to a lower (more negative) VON with increasing temperature is observed in the range of –50°C to +50°C, except for a TFT with an initial VON equal to zero, in which case the log10(ID) – VGS transfer curve is temperature-independent. A more detailed temperature-dependence assessment, however, indicates that the log10(ID) – VGS transfer curve shift is not exactly rigid since the mobility is found to increase slightly with increasing temperature. A noticeable anomaly is observed in certain log10(ID) – VGS transfer curves, especially when obtained at elevated temperature (e.g., 30 and 50°C), in which ID decreases precipitously near zero volts in the positive gate voltage sweep. This anomaly is attributed to a gate-voltage-step-involved detrapping and subsequent retrapping of electrons in the accumulation channel and/or channel/gate insulator interface. In fact, all IGZO TFT stability and temperature-dependence trends are attributed to channel interface and/or channel bulk trapping/detrapping.

Percolation Noise and Reduction Schemes in Submicron MOSFETs
Noise in deep -submicron and nanoscale transistors has reached a point where it is becoming a severe obstacle in ULSI design. Random telegraph signal (RTS) is a fundamental noise source that is wreaking havoc on circuits ranging from flash memory cells to CMOS image sensors. We attribute this noise to “Percolation Noise” as it is percolating currents in the channel which play a crucial role in creating such large noise signals. The ultimate goals of this research are twofold. First, is to gain a fundamental understanding of the source of the noise backed by experiment and theory. Second, using this fundamental knowledge, is to explore solutions for reducing the noise. The primary topic of this presentation will be the first goal of this research, followed by the research objectives for reducing and/or eliminating RTS noise which as to date has not yet been demonstrated.

Diversity Combining ARQ over the m (≥ 2)-ary Unidirectional Channel
In diversity combining automatic repeat request (ARQ), erroneous packets are combined together forming a single, more reliable, packet. In this thesis, we give a diversity combining scheme for the m-ary unidirectional channel. A system using the given scheme with a t-unidirectional error detecting code is able to correct up to unidirectional errors. To use the given scheme, the decoder should be able to decide the error type (increasing or decreasing). Hence, we also give simple techniques to make this decision for various unidirectional error detecting codes.

Dashboard Application for Experimentation Reporting Platform
In order to launch a new feature in Yahoo Search, we conduct experiments to measure the effectiveness of the new feature as compared to the existing production baseline features. Each experiment is conducted by sampling a small portion of cookies in the web search logs. The metrics are computed for each experiment by processing the data using statistical methods. The degree of significance is measured by comparing the metrics for each experiment against a baseline experiment. If the metrics are statistically significant, then the new feature is included in the production. This approach would help to improve the user experience on Yahoo Search. The main aim of the project is to build a reporting system that will allow the users to customize and select the metrics, monitor the robot activity and daily processing of data across different regions, export the metrics data in excel and text formats and provide an API to the third party vendors to get access to the metrics data. This system was tested on a small sample of employees and customers at Yahoo.

Directional Communications for 60 GHz Wireless Communications Networks
60 GHz wireless communications is an emerging research area with practical applications in multiple gigabit per second data transfers. However, in this higher frequency band, one faces additional challenges that are not present in traditional lower frequency networks. With the liberation of 60 GHz band into a license free spectrum, there has been a lot of interest in the research community to alleviate these challenges. Standardization body IEEE 802.15.3c Task Group also came up with a proposal for a channel model to be used in the 60 GHz networks. In this thesis, we propose several enhancements to the channel model proposed by IEEE. We incorporate the effects of different polarizations and study the effects of using them in different scenarios. We also propose a directional MAC algorithm based on the findings of the polarization study that will fully exploit the advantages of the polarization diversity in 60 GHz channel. Finally, we plan to provide a double-directional channel model for 60 GHz channel, which is missing in IEEE's proposed channel model. A double directional channel model is an essential tool to assess the performance of the directional MAC algorithm. We provide the performance analysis of these proposed methods using computer simulations.

Adaptive, Wideband Analog-to-Digital Conversion for Convergent Communication systems
The exponential rate of advances in modern communication devices in the last several years have brought us higher levels of functionality and performance as well as reductions in physical size and power consumption. To continue this rate of advancement, next generation systems require wider bandwidth and higher resolution ADCs.

Additionally, in order for ADCs to be used in a wide range of applications, reconfigurability and adaptability are critical features of future ADCs. Reconfigurable ADC architectures allow consolidation of receivers for multiple communication standards into one, providing size, power and functionality improvements over multiple discrete ADCs. This thesis presents a high performance track-and-hold block and reconfigurable high performance ADC for multi-functional communication applications.

In the design of analog-to-digital converters (ADCs), the front-end track-and-hold or sample-and-hold is often one of the most challenging parts of the design. Open-loop designs with high sample rates are reaching the limits of their linearity. Presented here is a high-speed, high-resolution closed-loop track-and-hold in a 0.18um SiGe BiCMOS technology. The architecture provides both high linearity and high speed, with 98.7dB and 89.4dB SNDR at 50MS/s and 100MS/s, respectively.

As these specifications evolve to meet customer demands, new, high performance ADCs are needed. To this end, an efficient parallel Delta-Sigma ADC architecture has been designed that achieves high performance in digital processes, while also providing additional architecture flexibility. This ADC, consisting of four parallel Delta-Sigma ADCs and a single pipeline ADC provides high performance and reconfigurablity. This ADC is suited to applications requiring not only wide-bandwidth, high resolution signal conversion but an on-the-fly reconfigurable resolution and bandwidth.

IXP2350 Network Processor Assisted PxP Data Distribution in LAN
Efficient data dissemination from a source to a large number of computers on the Internet is an important underlying mechanism for many applications, ranging from Internet video broadcast to software update applications. Development of P2P systems has provided a framework for efficient large scale data dissemination on the Internet by making use of peer’s bandwidth. While the P2P networks provide a scalable solution to this problem, the peer activities increase the load on the underlying physical network such as LAN and use more bandwidth. In this project, we show how a High Performance Network Processors-Intel IXP2350 can be integrated with the existing setup to (a) reduce the P2P traffic in the LAN and recover some bandwidth and (b) expedite the packet processing overhead using hardware customized for fast path processing, consequently minimizing delay and maximizing throughput.

Amorphous Oxide Semiconductors in Circuit Applications
The focus of this thesis is the investigation of thin-film transistors (TFTs) based on amorphous oxide semiconductors (AOSs) in two new circuit applications. To date, circuits implemented with AOS-based TFTs have been primarily enhancement-enhancement inverters, ring oscillators based on these inverters operating at peak frequencies up to ∼400 kHz, and two-transistor onecapacitor pixel driving circuits for use with organic light-emitting diodes (OLEDS). The first application investigated herein is AC/DC rectification using two circuit configurations based on staggered bottom-gate TFTs employing indium gallium oxide (IGO) as the active channel layer; a traditional full bridge rectifier with diode-tied transistors and a cross-tied full-wave rectifier are demonstrated, which is analogous to what has been reported previously using p-type organic TFTs. Both circuit configurations are found to operate successfully up to at least 20 MHz; this is believed to be the highest reported operating frequency to date for circuits based amorphous oxide semiconductors. Output voltages at one megahertz are 9 V and ∼10.5 V, respectively, when driven with a differential 7.07 Vrms sine wave. This performance is superior to the previously reported organic-based rectifier.

The second application is an enhancement-depletion (E-D) inverter based on heterogenous channel materials. Simulation results using models based on a depletion-mode indium zinc oxide (IZO) TFT and an enhancement-mode IGO TFT result in a gain of ∼15. Gains of other oxidebased inverters have been limited to less than 2; the large gain of the E-D inverter makes it well suited for digital logic applications. Deposition parameters for the IGO and IZO active layers are optimized to match the models used in simulation by fabricating TFTs on thermally oxidized silicon and patterned via shadow masks. Integrated IGO-based TFTs exhibit a similar turn-on voltage and decreased mobility compared to the shadow masked TFTs. However, the integrated IZO-based TFTs are found to be conductive and exhibit no gate modulation. Due to the conductive nature of the load, the fabricated E-D inverter shows no significant output voltage variation. This discrepancy in performance between the integrated and shadow-masked IZO devices is attributed to processing complications.

A Comprehensive Integration of First Year Engineering Education
Creating positive learning communities that engage incoming students with varying degrees of engineering experience poses a challenge to universities with higher numbers of students. The problem of introducing students to engineering has recently been approached by implementing novel lab structures, adjusting the lecture to incorporate current teaching techniques, or using orientation programs to build learning communities. These logistical or social orientation programs intend to build learning communities but typically neglect technical content necessary in building academically robust networks. This also loses an opportunity to build valuable technical self confidence within new students. In September 2006 a freshman mentor program started at Oregon State University which entails a full year mentor program for the entire incoming first year class. This program uses a trained cohort of undergraduate freshman mentors to connect a Platform for Learning with three terms of lectures and labs, changing a sequence of three distinct courses into a cohesive approach to technical skills in the first year of engineering education. Evaluation tools for the freshman mentor program consists of logged usage statistics from a freshman mentor database and statistically analyzed survey data collected throughout the year to track progress in mentoring effectiveness within the student body.

Broadband Modeling of Transformers on Silicon Substrates for RFICs
Magnetically coupled passive transformers are increasingly integrated on-chip for various analog and radio frequency (RF) applications including direct current (DC) isolation, impedance transformation/matching, and conversion between single-ended and differential signals. A primary motivation for the on-chip integration of transformers is the overall size reduction and reduced cost. However, the performance of on-chip transformers is adversely affected by increased losses in the conductors and silicon substrate as well as limited values of achievable inductance, coupling coefficient and quality factor. Consequently, accurate, broadband transformer models compatible with transient circuit simulation are needed for analog and RF integrated circuit design.

This thesis presents a new two-step methodology for automated broadband model generation for monolithic transformers integrated on silicon substrates. First, an equivalent circuit model (ECM) in single or multi-PI topology is extracted from available four-port scattering parameters obtained by electromagnetic full-wave simulation or measurement. To further enhance the broadband characteristics of the extracted ECM, an automated augmentation method based on linear least squares fitting is adapted. The new augmentation procedure adds physically motivated circuit elements to the ECM resulting in a guaranteed stable and passive circuit model with improved accuracy over a broad frequency range. The modeling algorithm has been implemented in a MATLAB code. A typical SPECTRE model extraction over the frequency range of 0.1-10 GHz takes less than 4 minutes on an Intel-based 2.13 GHz Xeon computer. The new extraction approach is validated for a variety of transformer configurations built on standard CMOS processes with stacked and interleaved topologies, different shapes, and various turns ratios, sizes and process parameters. The results show a significant improvement in accuracy compared to a previously developed extraction procedure.

High-performance and Low-Power Dynamic CMOS Circuits
Dynamic CMOS circuits are essential for the implementation of performance critical logic functions in high-performance digital integrated circuits because of their significantly high frequency of operation compared to that of static CMOS circuits. However, their speed advantage comes with a cost of higher sensitivity to noise, in addition to higher power dissipation, due to larger clock loading and higher leakage current in the modern process technologies. Register Files (RFs) and Content Addressable Memory (CAM) arrays, commonly used in high-performance integrated circuits, employ dynamic circuits for their read and comparison operations. In our thesis work, we propose to design power efficient dynamic circuits used in these memory arrays. We propose several low-power organizations of bit-lines in RF arrays. We will also present a low-power RF design approach using PMOS based evaluation circuits. Finally, we will describe the design of an area efficient eight-transistor novel CAM cell.

Time-Dependent Vector Field Design on 2-Manifold
Vector fields arise as a useful tool in a wide variety of applications in computer graphics and visualization applications. Designing and controlling vector fields, especially time-dependent vector fields, is necessary to many applications that involve systems changing over time. However, the existing vector field design systems can address only time-independent vector fields. I have observed a clear demand for such a set of techniques that allows the time-dependent vector fields to be created and modified. In the proposed research, I will address such a demand by two separate but consecutive projects. In the first project, I will focus on the topology of time-independent vector fields and propose efficient algorithms to compute it. In the second project, I plan to realize the first design tool for the creation and modification of a time-dependent vector field. These two projects will lead to the following contributions. First, the knowledge and techniques for vector field topology analysis will be enriched by the proposed research. Second, a design tool will be developed for creating and modifying a variety of time-dependent vector fields through topological and geometric analysis. The designed time-dependent vector fields can then be used in many computer graphics and visualization applications. To my best knowledge, this will be the first time-dependent vector field design tool for general purpose using topology.

A Wideband Low-Power Continuous-Time Delta-Sigma ADC
Delta-sigma ADCs are key building blocks in wireless communication systems due to their high dynamic range and excellent power efficiency. With increasing signal bandwidth requirements, the continuous-time delta-sigma ADC has become popular because it can achieve higher bandwidth or lower power dissipation compared to its discrete-time version.

In this thesis proposal, a new continuous-time cascaded delta-sigma ADC is presented, which can achieve 12 bit resolution within a 20 MHz signal bandwidth. The MASH 2-2 architecture is used for its good stability and high interstage gain. The low-distortion technique, which has been effectively used in discrete-time ΔΣ modulators, has been modified to reduce the excess-loop delay effect, and thus made applicable in continuous-time structures. A front-end passive low-pass filter is used to eliminate out-of band peaking, which is a common issue in continuous-time ΔΣ ADCs with feed-forward architecture. Finally, a digital compensation filter is designed to adaptively correct the quantization noise leakage due to the analog circuit noidealities. With a 90-nm CMOS technology, simulations indicate that the proposed ADC can achieve a 12 bit resolution with a 20 MHz signal bandwidth and a power dissipation around 25mW.

Learning MDP Action Models via Discrete Mixture Trees
This thesis addresses the problem of learning dynamic Bayesian network (DBN) models to support reinforcement learning. It focuses on learning regression tree models of the conditional probability distributions of the DBNs. Existing algorithms presume that the stochasticity in the domain can be modeled as a deterministic function with additive noise. This is inappropriate for many RL domains, where the stochasticity takes the form of a random choice over deterministic functions. This paper introduces a regression tree algorithm in which each leaf node is modeled as a finite mixture of deterministic functions. This mixture is approximated via a greedy set cover. To combat overfitting, pruning techniques incorporating log likelihood and KL-Divergence are employed. Experiments on three challenging RL domains, two with stochastic variants, show that this approach finds trees that are more accurate and that are more likely to correctly identify the conditional dependencies in the DBNs based on small samples.

Low-Power Double-Sampled Delta-Sigma ADC for Broadband Applications
High speed and high resolution Analog-to-Digital Converter is a key building block for wide-band wireless communications, high definition video applications and medical images. By leveraging the down scaling of the latest CMOS technology and the noise shaping properties, Delta-Sigma ADCs are able to achieve wide-band operation and high accuracy simultaneously. The design of a switched capacitor 12-bit Delta-Sigma ADC with a 20MHz signal bandwidth is presented here.

To achieve very low power consumption, this ADC utilizes the following three design techniques:

1. Double sampling to increase the effective over-sampling ratio.
2. Capacitor reset technique allows the use of only one feedback DAC to fully eliminate the quantization noise folding back.
3. High gain wide bandwidth two-stage opamps are designed to minimize the quantization noise leakage.

A 2+2 cascaded topology with 3-bit internal quantizer is used in this Delta-Sigma ADC to adequately suppress the quantization noise while guarantee the loop stability. This ADC is designed and will be fabricated soon in 90nm pure digital CMOS process. Simulated power consumption is less than 20mW with a power supply of 1.2V.

Substrate Noise Coupling in Ring VCO-Based Phase Locked Loops
In this thesis, the performance degradation of a phase-locked loop due to substrate noise is examined. A new analytical equivalent circuit model for substrate noise coupling is derived for a heavily doped silicon substrate. The model has been validated with measured data from a 0.35μm CMOS process. Since the model is physical, it can be used to predict substrate noise coupling without the need for extensive computer simulations using three-dimensional finite difference or Green's function solvers.

This is followed by an evaluation of the effect of substrate noise in a PLL. A PLL test chip fabricated in a 0.13μm CMOS process has been characterized over a wide range of substrate noise frequencies. The measured results combined with extensive simulations provide insight into the mechanisms for noise coupling in a PLL. Based on an understanding of the noise coupling, guidelines for minimizing the impact of substrate noise are presented.

Fluid Flow on Interacting, Deformable Surfaces
Fluid simulation is an interesting research problem with a wide range of applications including mechanical engineering, special effects in movies and games, and scientific simulation. Due to the complex nature of typical fluid flow equations, there are circumstances where a full volumetric fluid simulation may not be necessary to generate the desired effect. Fluid flow on surfaces, such as in the case of rain-drops or moving rivers, can be solved more effectively by using a surface simplification to the normally expensive 3D Navier-Stokes equations. We present such a system in which the user can guide fluid flow on surfaces that are not only deforming, but also colliding with other surfaces in an environment. We also describe a technique for rendering the fluid on surfaces as a height field, which allows nearly volumetric effects to be achieved through a computationally less expensive surface simulation. Such a framework, we believe, can be extended to allow interactive control and visualization of surface flows carving into surfaces.

Power performance of multiplication on multi-cores using in Cryptosystem
The Advent of multi-core makes people have dreams which same job will be done at double or more performance. Cryptographers also think that cryptographic operation on the multi-cores are more efficient than single-cores, since the cryptosystem uses long-bit words for their own crypto-algorithm. By using parallelizing the long-bit words operation on multi-cores, the cryptosystem can achieve a performance improvement.

However all long-bit words using in the cryptosystem are not suitable for on multi-cores. Especially long-bit words, in elliptic curves cryptography (ECC), are not fit to the multi-cores system word size. Our experiment shows some idle cores by fixed word size. The idle cores are vulnerable to cryptosystem analysts or hackers. They can guess what fields are used in cryptosystem.

In a cryptosystem, multiplication is most important part particularly in the public key cryptosystem. Long-bit word multiplication operations are needed for encryption and decryption. J. Fan et al proposed using Montgomery multiplication on multi cores [25, 26]. Fan’s Montgomery fit with the computer system words like 16-bit or 32-bit. Fan uses GF(2256) for an example. Fan’s Montgomery is suitable for RSA, however in ECC, it could cause some idle core depending on what GF is used in the cryptosystem. If we use unbalanced field which is not fit for system words like GF(2131), we will get an idle cores and needless power consumption. And also, the last word is always less then system-word size, i.e., 32 bits or 16 bits.

In this thesis, we will present a word-size adjustment technique for last words to fit multi-cores. By adjustment of word-size, we can improve performance and power efficiency using idle cores on fixed word sizes. And it also shows that inserting random instruction, which can confuse cryptosystem analyst, increases efficiency on multi-cores even though it adds some workload.

Power Efficient H.264 Video Decoding in Embedded Multiprocessor
This paper presents a novel methodology that enables power efficient video decoding in an embedded system based on MPSoC (Multiprocessor System on Chip). This methodology is a hybrid of the parallel processing which reduces power consumption of processors by exploiting thread-level parallelism and the Dynamic Voltage Frequency Scaling (DVFS) capability that utilizes slack time for each frame with processor granularity. The video decoding process must be well optimized to improve performance continuously due to the many complex computation units. Since these intense computation functions have their own specific patterns, they were mainly performed by specialized hardware devices. This kind of device, one that combines a main processor and an Intellectual Property (IP), still dominates the multimedia market place because of its adjustable performance, power, and convenience of manufacturing, even though the multi-core embedded processor was released a few years ago. Our approach exploits inherent advantages of the multiprocessor without additional hardware implementation, and presents a thorough analysis of multiprocessor in an embedded system. An application we target is H.264/AVC, a well-adapted video coding standard for current multimedia environment which is used for many portable devices. We improve performance and power reduction by using a unified approach that combines parallel processing and DVFS.

Automated Analysis, Design, and Optimization of Low Noise Oscillators
Low noise oscillators are universally needed in digital systems for clock generation and synchronization, and in radio-frequency communication front-ends for frequency up- and down-conversion. Noise in oscillators results in timing jitter, and limits the clock frequency of digital systems. In radio-frequency communication systems, phase noise in oscillators lowers the signal-to-noise ratio of transmitters and receivers, and degrades the overall bit-error-rate. Therefore, accurate simulation and optimization of oscillator noise performance is of utmost importance.

The focus of this dissertation is on automated analysis, design and optimization of low noise oscillators. Several advances in oscillator analysis that facilitate automated oscillator design and optimization are presented. These include a new sensitivity analysis for oscillators, a design-oriented circuit analysis technique, and an oscillator design optimization approach. The sensitivity analysis calculates sensitivities of an oscillator's periodic steady-state and perturbation projection vector to design, process, or environmental parameters. In the design-oriented approach to circuit analysis the circuit response is computed together with the values of circuit parameters that result in a desired circuit performance. These analyses form the foundation for an efficient oscillator optimization technique that is general and applicable to all oscillator types.

Fast Handoff in WLAN and Behavior Based Mobility Prediction
Wireless Networks have been widely adopted into a major part of today's network infrastructure. They have become a popular technology to not only expand the coverage of wired networks but also to interconnect a large wireless networks, i.e., wireless mesh networks.

As they allow more flexible communication than traditional wired-networks some challenges are raised, such as maintaining a seamless connectivity when MSs move across the cells and dynamically adjusting resources for the transit MSs. Many solutions have proposed using mobility prediction to allow network devices and applications to prepare and adjust before the actual movement. However, none of the existing work considers mobility related to human factors.

Therefore, this thesis proposes a technique called Behavior-based Mobility Prediction (BMP) that captures the dynamic behavior of MSs and the network by considering location, group, time-of-day, and duration factors. The proposed BMP is targeted to provide accurate next-AP predictions for WLANs to minimize the handoff latency.

Moreover, the prediction can also apply to resource allocation in any type of Wireless Networks. Our simulation study shows that BMP virtually eliminates the need to scan for APs during handoffs and results in much better overall handoff delay compared to existing methods.

Digital Pulse Shape Discrimination Methods for Triple-Layer Phoswich Detectors Using Wavelets and Fuzzy Logic
A two-channel data acquisition system for simultaneous detection and discrimination of beta particles and gamma rays has been developed. Each channel measures and analyzes the input pulses which are the result of the absorption of radiation in the layers of the detector. The detector is a triple-layer phoswich (phosphor sandwich) scintillation detector followed by a photomultiplier tube (PMT). The PMT amplifies the photons and converts the photons to an electric signal. The signal is digitized and sent to the host computer for further processing. Two new digital algorithms based on Fuzzy Logic and on the Continuous Wavelet Transform have been developed and are discussed in this thesis.

In the first method, a de-noising algorithm based on the Wavelet Transform is implemented to reduce the effect of noise introduced by the noisy analog channel and by the photomultiplier tube. Three new timing features are extracted and given as input to a fuzzy interface system. The main goal of fuzziness in data set is to reduce the system complexity and to provide a model that allows for approximate results. Compared to the non-fuzzy method which was originally implemented for this detector, the fuzzy algorithm shows a better performance in separating beta and gamma spectra, especially at high energies. Also absorption in multiple layers is detected more efficiently.

The second algorithm is based on the Continuous Wavelet Transform. The novelty of this method consists in using scale-domain features. Since the output pulse shape of the photomultiplier tube is a non-stationary signal, conventional Fourier methods are not efficient for analyzing these signals and most of the existing pulse shape discrimination methods use time-domain features. Therefore, a time-frequency space is better suited to analyze these non-stationary signals. This method shows a better performance over existing time-domain methods in terms of robustness to noise and reliability.

The simultaneous detection of beta particles and gamma rays has several applications (for instance detection of underground nuclear explosions). The methods presented in this thesis could also be used in alpha/beta/neutron/gamma discrimination systems for cancer diagnosis and treatment.

1/f Noise Of GaAs Resistors On Semi-Insulating Substrates, And 1/f Noise Due To Temperature Fluctuations In Heat Conduction
This research work focuses on the mechanism of 1/f noise in GaAs resistors on semi-insulating substrates and 1/f noise due to temperature fluctuations in heat conduction in bipolar transistors. The goal of this research is to generate accurate models to explain physical origin of 1/f noise in semi-insulating substrate and semiconductor devices dissipating high power.

The model is based on a distributed equivalent circuit representation of the substrate, and shows that 1/f noise is a bulk phenomena associated with high resistivity substrates. One consequence of the theory is that in this particular instance Hooge's parameter is given by a formula.

Power dissipation at high currents and voltages in semiconductor devices results in significant heat generation and heat conduction towards the heat sink. The device temperature is only an average value and there are as a consequence of the diffusion equation for heat flow itself temperature fluctuations about this average value. It will be shown that these temperature fluctuations can result in 1/f noise at moderately low frequencies where these frequencies are determined by the physical dimensions over which the heat flows and the diffusion transit time. The results are then related to the shot noise or white noise due to the collector current allowing a determination of the 1/f noise corner frequency.

Thread Level Speculation for Multicore Systems
Thread Level Speculation (TLS) has been an intense research subject due to its ability to overcome the limitations of exploiting Instruction Level Parallelism (ILP) on high-performance, superscalar processors. One method of exploiting TLS is through Dynamic Speculative Multithreading (D-SpMT) that extracts multiple from a sequential program without compiler support or instruction extensions. The presentation will discuss the performance evaluation of a D-SpMT architecture called Cascadia, which uses an asymmetric multi-core architecture and provides multi-grained thread-level support in order to maximize TLP performance. Based on the results and knowledge gained through the validation of Cascadia, our future goals are to extract TLS automatically from the source code. This allows us to test a wider range of applications on existing technologies without the need for complex hardware implementations.

Automated MS Word Reformatting Tool for DAS
For disabled students, having accessible class materials is critical for their success in education. Disability Access Services at Oregon State University responds to the needs of these students and provides a service to reformat the materials to a suitable format for each student. One of these formats is a word document in a format that can be read by a text reader.

The purpose of this project is to automate the reformatting process for word documents that are used by the visually impaired students at Oregon State University. The automated process makes the reformatting process more efficient and less prone to human errors. The reformatting result also complies with the international accessible standards, DAISY and NIMAS.

Network Coding Techniques for Multimedia Transmissions
Multimedia streaming over lossy packet networks, such as wireless networks or the Internet, is challenging due to a number of factors, including high bit rates, delay sensitivity, loss sensitivity, and inter-dependency of media data. As such, there are many media streaming solutions ranging from source coding and channel coding to transport protocols. Recently, network coding has been introduced to efficiently utilize the throughput of multicast networks. This research investigates the application of network coding for multimedia streaming over wireless networks and the Internet. In particular, this research demonstrates that: (1) network coding can improve the multimedia multicast throughput, and (2) network coding can be integrated with a number of scheduling algorithms to maximize the multimedia quality. A number of simulations in some streaming scenarios will be presented to confirm the advantages of network coding.

Random Telegraph and 1/f Noise in Deep-submicron Metal-Oxide-Semiconductor Transistors
Random Telegraph noise has become a major concern now that MOS transistors in standard production are well below the 100nm node. Device performance in memories, analog circuits, and rf circuits are negatively impacted by the increasing RTS noise. We will describe the physical aspects of the noise and the effects RTS has on circuits. A few techniques have been proposed to reduce RTS noise in various circuit applications but many of these techniques are far short of being a complete solution. This research focuses on novel RTS noise analysis and remediation techniques not yet demonstrated. One proposed modification which is showing promise is to modify the doping in the active region. Further work remains on the doping dependence of the RTS noise which is just one aim of this research.

Gender HCI and Problem-Solving Strategies
Problem-solving software is meant to support both male and female users, but evidence is beginning to emerge that it does not. We suspect that the reported gender differences go deeper than mere features to the strategies themselves, and this is what we propose to investigate. Attending to strategies users would like to use when accomplishing a problem-solving task is foundational knowledge that is necessary for designing software features that genuinely support the users they are trying to reach. Yet, there has been no real attention to end users’ problem-solving strategies in the past, males’ or females’. This thesis proposes to help fill this critical gap by examining where strategies fit in the overall problem-solving process (using the sensemaking model), what underlying factors might affect strategy adoption (ex. epistemological style, self-efficacy, information processing style), and how these strategies can best be supported through problem-solving software features.

Development of a Barcode Integrated SQL Database Web Application in Tree Genetic Research Lab
Genetic engineering and genetic modification are techniques used to introduce new characteristics to an organism in order to increase its usefulness. The application of genetic engineering techniques to plants has produced beneficial consequences, such as an increase of Vitamin A level in rice, improvement of plant resistance to insects and herbicides, and alteration of plant chemistry to facilitate pulp production in the tree industry. Tree Biosafety and Genomics Research Cooperative (TBGRC) is a National Science Foundation Industry/University Research Center aiming at developing genetic technologies based on research in plant molecular biology that have potential applications to forest industries. Its research is presently focused on genetic engineering and functional genomic studies. Key research themes include genetic control of flowering, environmental analysis of transgenic plantations, and use of gene transfer for functional genomics. The core facility in TBGRC to carry out the research is the tissue culture laboratory, where the transgenic plants containing modified genes are produced. A barcode-integrated Web application was developed to facilitate the tissue culture processes in the laboratory. The whole system is comprised of three units: the barcode system, an SQL database, and a Web application implemented in C#/ASP.NET. The barcode system consists of BarFontTM barcode generating software, a barcode label printer from Zebra Technologies, and an IMAGETEAMTM 3800 hand held barcode scanner. The relational database data schema contains six tables and 39 data fields in which the unique barcode functions as an identity key for each tissue culture group. The barcode-integrated Web application consists of 11 major Web pages, with summarized function in the following table:

The barcode-integrated Web application greatly increases the efficiency of the tissue culture process. The application can, 1) provide a report of tissue culture experiments performed during a specific period to facilitate experiment planning and medium preparation at different steps in plant regeneration; 2) provide a history of an individual tissue culture group; 3) provide information on transgene origin (DNA construct, Agrobacterium strain) of transgenic plants involved in current experiments; 4) enable information to be conveniently and efficiently recorded in the lab by entering data via computer and retrieved by scanning bar code label; 5) quickly sort and summarize information regarding experiments in process based on criteria such as constructs, protocol, and projects, and generate various types of data reports. Eleven users in TBGRC have used the application and more than 1,100 transgenic plants have been generated using the application. Two new protocols for genetically transforming plants are under development using the application. The application reduces work burden and increases efficiency and accuracy of data recording and tracking. As a research program it significantly facilitates data analysis and evaluation. Overall the application has been proven to be an excellent assistant to the TBGRC tissue culture laboratory.

Low Power High-speed Pipelined ADCs
Real world is analog but the processing of signals can best be done in digital domain. So the need for Analog to Digital Converters (ADCs) is ever rising as more and more applications set in. With the advent of mobile technology, power in electronic components is being driven down to get more battery life. And because of their ubiquitous nature, ADCs are prime blocks in the signal chain which people have turned to to reduce power. In this research on Low Power High-speed Pipelined ADCs, two techniques to reduce power have been proposed. The first is the Capacitor and Opamp Sharing Technique and the second is the Hybrid architecture which makes use of asynchronous conversion concepts. The first technique has been implemented in Silicon and the measurement results which prove the technique will be presented. The second concept is in design stage and will be fabricated soon.

Effective Training and Feature Induction in Sequential Supervised Learning
Sequential supervised learning problems arise in many real applications. This thesis focuses on two important research directions in sequential supervised learning: feature induction and efficient training.

In the direction of feature induction, there will be two major contributions. First, I will further analyze the performance of the TreeCRF algorithm, a major CRF training algorithm that can induce nonlinear features in the training process. I will also study the problem of handling missing input values in CRFs, which has been rarely discussed in the literature. Two missing values methods specific to TreeCRF algorithm will be compared with two standard methods, and a guideline will be given as to which method is preferred in a given situation. Second, I will provide a new general method to induce nonlinear features for margin based classifiers instead of using the kernel trick. This will be done by optimizing unconstrained primal loss functions directly with functional gradient tree boosting. This method will be applied both to ordinary SVMs and to margin based structured classifiers, and it is expected to achieve comparable performance with faster training speed.

In the direction of efficient training, I will provide further understanding of two existing efficient learning frameworks: sequential error-correcting output coding and search based structured learning. I will discuss the limitations of these two frameworks and provide possible improvements for each.

Solving Multiagent Assignment Markov Decision Processes
Multiagent Assignment Markov Decision Processes are special cases of MDPs where several collaborative agents are assigned tasks by a centralized controller. I propose a method based on decomposing the action selection into an upper assignment level and a lower task performance level. The assignment problem is solved by search, while the lower task level is solved through reinforcement learning. In addition, I show how previous work on coordination graphs can be used for coordinating the agents at the lower level. I present empirical results in a large Multiagent predator-prey domain demonstrating that both assignment level search and task level coordination can together outperform either method alone.

High Efficiency Delta-Sigma Modulation Data Converters
Enabled by continued device scaling in CMOS technology, more and more functions that were previously realized in separate chips are getting integrated on a single chip nowadays. The mature integration on silicon has opened the door to new portable wireless applications, and initiated a widespread use of these devices in our common everyday life. Wide signal bandwidth, high linearity and dynamic range, and low power dissipation are required of embedded data converters that are the performance-limiting key building blocks of those systems. Thus, power-efficient and highly-linear data conversion over wide range of signal bands is essential to get the full benefits from device scaling. This continued trend keeps relentless innovation in the design of data converter continuing.

Traditionally, delta-sigma modulation data converters proved to be very effective in applications where high resolution was necessary in a relatively narrow signal band. There have been active research efforts across academia and industry on the extension of achievable signal bandwidth without compromising the performance of these data converters. In this dissertation, architectural innovations, combined with effective design techniques for delta-sigma modulation data converters, are presented to overcome the associated limitations. The effectiveness of the proposed approaches is demonstrated by experiments with the following state-of-the-art prototype designs: (1) a 0.8 V, 2.6 mW, 88 dB dual-channel audio delta-sigma modulation D/A converter with headphone driver; (2) an 8.1 mW, 82 dB self-coupled delta-sigma ADC with 1.9 MHz bandwidth and -97 dB THD; (3) an 88 dB ring-coupled delta-sigma ADC with 1.9 MHz bandwidth and -102.4 dB THD, (4) a multi-cell noise-coupled delta-sigma ADC with 1.9 MHz bandwidth, 88 dB DR, and -98 dB THD; (5) a noise-coupled time-interleaved delta-sigma ADC with 4.2 MHz bandwidth, -98 dB THD, and 79 dB SNDR; (6) a noise-coupled time-interleaved delta-sigma ADC with 2.5 MHz bandwidth, -104 dB THD, and 81 dB SNDR. As an extension of this research, two novel architectures for efficient double-sampling delta-sigma ADC and improved low-distortion delta-sigma ADC are proposed, and validated by extensive simulations.

A Survey of Continuous-Time ΔΣ Modulators
Recently, delta-sigma modulation has become a widely applied technique for high-performance analog-to-digital conversion of narrow-band signals. Most of the early designs used discrete-time structure for good accuracy and good linearity. The transfer functions are independent of the clock frequency. However, high unity-gain bandwidths of the opamps are required to satisfy the settling accuracy required in the discrete-time designs. Continuous-time structure can potentially achieve higher clock frequency with less power consumption. the anti-aliasing filter can also be eliminated due to the anti-aliasing property of CT modulators. On the other hand, CT ADC have their own problems, such as jitter sensitivity and excess loop delay.

In this thesis, the state-of-the-art of CT modulator is reviewed. The problems in the design of CT ADCs are analyzed and solutions to them are described. The theory, design and implementations of CT modulator will also be reviewed.

An Implementation of a Reliable Broadcast Scheme for 801.11 Using Network Coding
Forward Error Correction and retransmission are two approaches used to reliably broadcast data in a network with poor quality of service. Taking some assumptions, it has been suggested that a retransmission based reliable broadcasting scheme using network coding should in theory provide an increase in bandwidth efficiency by combining packets as they are retransmitted. In this thesis, we remove those assumptions by providing two algorithms to implement the previously proposed scheme. These two algorithms differ in a way that allows them to compare the tradeoffs between two different methods of packet loss notification. We test these two algorithms over several parameters and provide insights into the cause of their performance attributes.

Data Processing and Visualization for Anomaly Detection in Web-Based Applications
Web applications are popular attack targets. Misuse detection systems use signature databases to detect known attacks. However, it is difficult to keep the database up to date with the rate of discovery of vulnerabilities. They also cannot detect zero-day attacks. By contrast, anomaly detection systems learn the normal behavior of the system and monitor its activity to detect any deviations from the normal. Any such deviations are flagged as anomalous. This thesis presents an anomaly detection system for web-based applications. The anomaly detection system monitors the attribute value pairs of successful HTTP requests received by webserver applications and automatically creates parameter profiles. It then uses these profiles to detect anomalies in the HTTP requests. Customized profiles help reduce the number of false positives. Automatic learning ensures that the system can be used with different kinds of web application environments, without the necessity for manual configuration. The results of the detection are also visualized, which enable the system administrator to quickly understand the state of the system and respond accordingly.

Training Design and Power Allocation for Closed-Loop Multi-Antenna Systems with Limited Feedback
The multi-input and multi-output (MIMO) wireless systems have been being an active research area in recent years because of their large multiplexing gain and diversity gain comparing with single-antenna systems. Although non-coherent MIMO systems do not need the channel knowledge at the receivers, but they incur high decoding complexity which limits their applications. Coherent MIMO systems need channel knowledge at the receivers and sometimes at the transmitters (e.g., in transmitter beamforming, precoding, power loading) to explore above gains. Three topics are presented in this proposal. First, in a practical beamforming system where the feedback channel is not error-free, the scheme to minimize the error effect is proposed. Second, in a training-based closed-loop MIMO system where the receiver acquires channel knowledge by training and feedbacks the channel knowledge to the transmitter, the optimal training design is proposed to maximize a lower bound of closed-loop capacity. At last, as the further work of the research, the time-selective block fading MIMO channel model will be considered where the training design will be optimized by taking the correlation between consecutive blocks into account.

Performance Evaluation of Hybrid Peer-to-Peer System for Streaming
Finding an efficient way of distributing content in Peer-to-Peer (P2P) networks has become important with the growing popularity of media streaming applications. Video multicast applications rely on the efficiency of content distribution from a single source to multiple receivers where one source streams a video to a large number of destination nodes through an overlay multicast tree consisting of peers.

The topologies of these P2P networks do not make efficient use of the bandwidth of the participating nodes. The Hybrid Peer-to-Peer architecture (Hypp) provides an application layer mesh that exhibits near optimal throughput by having all nodes, including the leaves, contribute to the overall system throughput. This project presents the experimental results of a real world P2P system based on the Hypp topology deployed on PlanetLab nodes. The Hypp architecture achieves near optimal throughput while provides scalability, low delay and bandwidth fairness among peers.

Automated Model Parameter Extraction for Noise Coupling Analysis in Silicon Substrates
An automated process, requiring the fabrication of a small set of test structures, efficiently extracts the coefficients of Z-parameter based macromodels. The extraction process has been validated for both heavily and lightly doped substrates and can be applied to a variety of technologies. After the parameters of a macromodel have been extracted, the model can be used to quickly and accurately calculate the equivalent substrate network connecting an arbitrary number of contacts.

This automated extraction process has been integrated into the Cadence DFII environment to provide a seamless flow for substrate noise analysis.

Efficient Power Conversion Interface Circuits for Energy Harvesting Applications
Power harvesting from the environment for powering micro-power devices have been increasing in popularity. These types of devices can be used in embedded applications or in sensor networks where battery replacement is impractical. In this dissertation, different methods of harvesting power from the environment are explored to obtain alternatives for battery powered devices. Some of the most popular energy extraction methods used in these devices is radio frequency (RF) and piezoelectric energy extraction.

New power conversion circuits to interface to a piezoelectric micro-power generator have been fabricated and tested. Circuit designs and measurement results are presented for a half-wave synchronous rectifier with voltage doubler, a full-wave synchronous rectifier and a passive full-wave rectifier circuit connected to the piezoelectric micro-power generator. The measured power efficiency of the synchronous rectifier and voltage doubler circuit fabricated in a 0.35-μm CMOS process is 88% and the output power exceeds 2.5-μW with a 100-kΩ, 100-nF load. The two full-wave rectifiers (passive and synchronous) were fabricated in a 0.25-μm CMOS process. The measured peak power efficiency for the passive full-wave rectifier circuit is 66% with a 220-kΩ load and supplies a peak output power of 16-μW with a 68-kΩ load. Although the active full-wave synchronous rectifier requires quiescent current for operation, it has a higher peak efficiency of 86% with a 82-kΩ load, and also exhibits a higher peak power of 22-μW with a 68-kΩ load which is 37% higher than the passive full-wave rectifier.

Current RF-powered devices are typically inductively coupled and extract their energy from the near field while operating within a few inches of the radiating source. Longer operating distances, exceeding 10 meters, is desired for a broader set of applications including distributed sensor networks. This dissertation describes an efficient method for far field power extraction from RF energy to enable long-distance passively powered sensor networks. An RF-DC power conversion system is designed to efficiently convert far-field RF energy to DC voltages at very low received power. Two passive rectifier circuits are designed in the TSMC 0.25μm mixed-signal CMOS process and the antenna for the system is printed on a 4-layer FR4 board with a carefully controlled trace impedance. A high-Q resonator is used with a matching network to passively amplify the input voltage to the rectifier. At the circuit level, floating gate transistors are used as rectifying diodes to reduce the diode threshold loss in voltage rectification and therefore increase the rectifier efficiency.

With the 36-stage rectifier, the system can attain maximum efficiency of 60% at 3 meters distance and can rectify input voltages as low as 50mV and has passive voltage gain of 6.4. This system operate at 2.5V at received power as low as 5.5μW (-22.6 dBm), corresponding to 44 meters operating distance. For distances of 15 meters, 1 volt DC is measured with 0.3μA load current at 906 MHz.

PPTAssist, A tool help user reuse slides and a framework for applying information retrieval techniques over presentation documents
Over time, individuals and workgroups accumulate large collections of presentations. Few create new presentations from scratch, rather they use past presentations as templates and cut and paste previously created components on slides into a new presentation.

However, frequently this process is costly and error-prone. Tools that help create presentations more effectively and efficiently by reusing past presentations could substantially decrease the time we spend creating presentations. Yet currently there are no tools to provide good support for this specific activity. PPTAssist is a tool developed to promote reuse activities by extracting meaning association between slides in a given document corpus and recommend possible reusable slides for given authoring tasks. It is also designed to serve as a framework for comparing retrieval techniques for recommending slides. In the project, different associating and ranking algorithm are tested and the implementation techniques involving the construction and design aspects are discussed. During the talk, you will also see a live demo of the PPTAssist software.

Improved Design Techniques for Analog and Mixed Circuits
Although the digital revolution can realize many of past analog components in the digital forms, our world is surrounded with analog signals such as voice, temperature, etc. The bridge between these two worlds is one of key performance limitations among overall systems and it includes analog filters and data converters.

This thesis studies two design techniques with respect to the improvement of the performances of the bridge circuits; one is an implementation of the delta-sigma A/D converter with a new architecture and another is a proposed correlated double-sampling technique for continuous analog filters. A circuit implementation for the new architecture converter is proposed and implemented in AKM 0.18µm CMOS technology. The test results show that the modulator achieves 72dB of SNDR from the 1.8 V supply voltage. A newly proposed correlated double sampling technique compensates the gain error of a high-Q Tow-Thomas filter which originates from the op-amp imperfections. The gain error is reduced to 0.6dB from 2.5dB with the correlated double sampling technique.

Supporting the Learning Process of Open Source Novices: An Evaluation of Code and Project History Visualization Tools
Active participation and collaboration of community members are crucial to the continuation and expansion of open source software projects. Researchers have recognized the value of community in open source development and studied various aspects of it including structure of communities, motivations for participation, and collaboration among members. However, the majority of previous work is devoted to active contributors and little is known about newcomers to open source projects. In an attempt to bringing more attention to these potential contributors to open source and supporting their joining process by enhancing their initial learning experience, we investigated the information needs of those who are considering joining an open source project as developers and use of software in fulfilling the needs and providing information that are important to perform software development/maintenance tasks. Our controlled experiment has revealed that the tools and resources available from current open source projects are lacking in providing information that is embedded in development artifacts such as discussion archives, trackers, and source code.

Difficulty obtaining such information may have a negative impact on newcomers' motivation on learning and further their engagement in activities. Our investigation of information visualization in support of learning suggests that providing visual information to newcomers may alleviate the difficulties associated with managing a large amount of information and enhance their learning experience.

Design-oriented steady-state and sensitivity analysis and optimization of autonomous circuits
Fast analysis and optimization techniques for autonomous circuits are presented in this thesis. New design-oriented large-signal circuit analyses and the small-signal sensitivity analyses for oscillators have been developed. The design-oriented analyses efficiently find values of circuit parameters that result in a desired circuit performance given by a set of equality constraints. These analyses enable formulation a more compact optimization problems. The new sensitivity analysis for oscillators provides feasible search directions, such that at each step in an optimization procedure the design equality constraints are satisfied.

Efficient VLSI Architectures for MIMO and Cryptography Systems
Multiple-input multiple-output (MIMO) communication systems have recently been considered as one of the most significant technology breakthroughs for modern wireless communications, due to the higher spectral efficiency and improved link reliability. The sphere decoding algorithm (SDA) has been widely used for maximum likelihood (ML) detection in MIMO systems. It is of great interest to develop low-complexity and high-speed VLSI architectures for the MIMO sphere decoders.

The first part of this dissertation is focused on the low-complexity and high-speed sphere decoder design for the MIMO systems. It includes the algorithms simplification, and transformations, hardware optimization and architecture development. Specifically, we propose the layered reordered K-Best sphere decoding algorithm and dynamic K-best sphere decoding algorithm, which can significantly improve the detection performance or reduce the hardware complexity. We also present the efficient K-Best sorting architecture, which greatly simplifies the sorting operation of the K-Best SDA. In addition, we introduce the early-pruning K-Best SD scheme, which eliminates the unlikely candidate at early decoding stages, thus saves computational complexity and power consumptions. For the conventional sphere decoder design, we develop the parallel and pipeline interleaved sphere decoder architecture, which considerably increases the decoding throughput with negligible extra complexity. Finally, we design the efficient radius and list updating units for the list sphere decoder, which increases the speed of obtaining the new radius and reduces the complexity for generating the new candidate list.

The wireless communication technologies are widely used for the benefits of portability and flexibility. However, the wireless security is extremely important to protect the private and sensitive information since the communication medium, the airwave, is shared and open to the public. Cryptography is the most standard and efficient way to protect the securities.

The second part of this thesis is thus dedicated to the high-speed and efficient architecture design for the cryptography systems including ECC and Tate pairing. We propose an efficient fast architecture for the ECC in Lopez-Dahab projective coordinates. Compared with the conventional point operation implementations, the point addition and doubling operations can be significantly accelerated with reasonable hardware overhead by applying parallel processing and hardware reusing. Moreover, we develop a complexity reduction scheme and an overlapped processing architecture for the Tate pairing in characteristic three. The proposed architecture can achieve over 2 times speedup compared with conventional sequential implementations for the Duursma-Lee and Kwon-BGOS algorithms.

Re-finding Documents Using Provenance Information with TaskTrail
Recent research suggests that file attributes such as title, location, size, and time of last use are poorly remembered by users, yet these attributes are arguably the most frequently utilized by existing desktop search tools. This paper describes a search tool which takes an entirely new approach, enabling users visualize the relationships between documents and thereby re-find documents via their provenance relationships to other documents.

Activity Recognition in Desktop Environments
Knowledge workers are struggling in the information flood.

There is a growing interest in intelligent desktop environments which help knowledge workers organize their daily life. Intelligent desktop environments allow the desktop user to define a set of "activities" that characterize the user's desktop work. These environments then attempt to identify the current activity of the user in order to provide various kinds of assistance. TaskTracer is one of these efforts. Our previous work on activity recognition has shown some fairly good results. However, possible improvements do exist. First, there could be different levels at which we can describe an activity, and until now we have only focused on the highest level. Second, our current predictor follows the standard "bag-of-words" approach, and rich relational information was ignored.

To address the above issues, we propose to classify activities into three levels: "task" as in TaskTracer, workflow, and operation. In this proposal, we concentrate on the two higher levels of activity -- "task" and "workflow" -- and we propose an activity recognition solution for each of them. To recognize tasks, we propose a discriminative training approach. This approach employs relational features and adopts the Passive-Aggressive Algorithm (PA) for online training. To recognize workflows, we formally describe the problem and analyze its complexity. The data consists of interleaving instances and is relational in its nature. These pose a challenge for the recognition and make it necessary to do some approximations. We propose several possible solutions based on different approximation assumptions. In the end, we discuss the research contribution and present the research plan.

Satellite Image Processing and Web-Based Services Implementation
The objective of this paper is to document the image-processing pipeline and visualization tools used to organize and process data returned from the High Resolution Imaging Experiment (HiRISE) and the context camera (CTX) on board the Mars Reconnaissance Orbiter (MRO). The image processing tools ISIS and GDAL were used to convert raw data to various image formats as requested by mission scientist. A web-based interface was created to make the images publicly available throughout JPL. The centralized imagery server enables users to access a consistent set of imagery data through a standard interface, and to provide a single repository to update when new images become available.

Novel Design and Implementation of a Permanent Magnet Linear Tubular Generator for Ocean Wave Energy Conversion
The world's energy consumption is growing at an alarming rate and the need for renewable energy is apparent now more than ever.

Estimates have shown that optimization of the extraction of energy from the ocean could significantly aid the world's quest for sustainable and affordable energy services for all. From small power data buoys to generating power for coastal communities, everyone stands to benefit from the technological optimization of ocean wave energy devices. This thesis explores the design and implementation of a novel permanent magnet linear generator for direct drive ocean wave energy extraction point absorber buoys. The design optimizes the armature and magnet sections of a permanent magnet linear tubular generator (PMLTG) for the purposes of maximizing the energy conversion efficiency while minimizing cogging forces. Cogging forces in a linear generator influence power fluctuations and hydrodynamic performance of the wave energy extraction system. Implementation techniques involving the construction and mechanical design aspects are included.

Joint Maximum Likelihood Estimation of Timing and Frequency Offset in OFDM System
OFDM system is a popular multi-carrier modulation scheme that is robust to frequency selective fading, highly spectral efficient and capable of achieving high data rate. However, it is very sensitive to timing and frequency offset. This report proposes a cyclic-prefix based joint Maximum Likelihood estimation of timing and frequency offset. Our method does not need a training sequence and thus can significantly reduce transmission overhead. The simulation results also show our estimator has a much better performance than the conventional method.

Power Reduction of MPEG Video Decoding for Mobile Multimedia Systems
The purpose of this thesis is to explore methods which can reduce the power dissipation of a mobile system while decoding MPEG video. MPEG decoding is a microprocessor intensive process that makes heavy use of both the L1 and L2 caches as well as main memory. The heavy load placed on the system during the MPEG decoding process results in large dynamic power losses caused by both the execution of instructions and the flow of data into and out of the caches and main memory. To reduce the power dissipation of the system during MPEG decoding, multiple techniques were applied to control the flow of data and make the decoding process more efficient. The system was simulated with different L2 cache sizes to determine which sizes resulted in the best power improvements while maintaining acceptable performance levels.

A fast IDCT algorithm was implemented to improve the efficiency of the decoder during the computationally heavy IDCT phases. Finally, selective caching was introduced to the system to further reduce the traffic between the caches and main memory. These techniques were simulated on the Sim-Panalyzer simulator using a similar system configuration to one found in a typical mobile media device. These methods coupled with proper L2 cache sizing produced power reductions of 50-60% over the baseline system.

High Speed, High Resolution Track-and-Hold and Efficient Parallel Delta-Sigma ADC
This work presents an efficient implementation of a parallel delta-sigma analog-to-digital converter. The parallel architecture uses four delta-sigma based channels, each consisting of a 2-1-1 MASH architecture, as well as a shared 8-bit pipelined quantizer. The architecture provides high speed and high resolution with flexibilty to dynamically adjust resolution and bandwidth and to perform some basic signal processing at the front end. This converter achieves 15 bit SNR over a 12.5 MHz signal bandwidth, with an oversampling of 4X in simulation. The chip is designed in a TSMC 0.25um process. The design of high-speed, high-resolution track and hold blocks can be a limiting factor in the data converter design. Also presented will be a high-speed, high-resolution closed loop track and hold in 0.18um SiGe BiCMOS technology. The architecture presented provides 15 bit linearity and >100MS/s while reducing the input loading by a factor of 10X compared to conventional closed-loop designs.

Mining Behavioral Patterns from HCI Data
The main aim of the project is to find users strategies and behavior patterns from the human computer interaction log data. We focus on extracting general strategies from the log data and associating them strategies with users gender and problem solving success. The HCI application in our study is the gender HCI project, which uses a problem-solving prototype software called forms/3. We applied sequential pattern mining to the log data and obtain user action patterns while using the software. We find that the obtained individual patterns fail to provide general strategies used by the users and are redundant in structure. This led us to examine different ways of clustering the patterns. The group of clusters obtained helped us find interesting strategies that appear to be related to users gender and success in problem solving.

Visualization and Analysis of Species Diversity in the HJ Andrews Experimental Forest
Often current scientific research suffers from an effective presentation environment. Sometimes software tools will be developed only for specific research datasets and are often impractical for others. This paper explores the use of Google Earth as a visualization environment and discusses the author's project for generating Kml and related files. Kml files describe geospatial information and define how it is presented within Google Earth. As a proof of concept, two distinct datasets from the HJ Andrews Experimental Forest are used as the basis for this paper. The first dataset is on spatial distribution of exotic plant species. The second dataset is on the spatial and temporal distribution of moths. Variations in the presentation and analysis of each dataset, along with the project implementation details will be discussed.

Kinematic and Cyclostationary Parameter Estimation for Co-Channel Emitter Location Applications
The problem of locating a signal source, or an emitter, has many civilian and military applications, such as communication regulations enforcement, military reconnaissance, and search-and-rescue operations. Many of the most widely used emitter location methods rely on the accurate and robust estimation of the differential time delay, or time-difference-of-arrival (TDOA), and the differential Doppler shift, or frequency-difference-of-arrival (FDOA), between signal replicas arriving at two spatially separated receivers. There are many conventional methods for estimating TDOA and/or FDOA. However, these methods are unable to produce unbiased TDOA and FDOA estimates when multiple emitters are located spatially close to each other. In many cases, the spatial proximity at which the conventional methods fail is still too large to ignore for precision emitter location applications. This problem is made even more difficult when the signals from the emitters share the same regions of the spectrum at the same time.

When spatially close emitters overlap spectrally and temporally, robust TDOA and FDOA estimation is difficult, and accurate emitter location jointly requires both the estimation of TDOA, or FDOA, or both, as well as the estimation of a signal parameter that can be used to separate the signal-of-interest (SOI) from a signal(s)-not-of-interest (SNOI) that are within the receiver's field of view. The signal separation parameter selected depends on the type of signal modulation. In this thesis, the signals of interest are bauded signals. The separation methodology for such signals is cyclostationarity with parameterization by cyclic frequency. Based on this assumption, a new three-dimensional joint estimation method for TDOA, FDOA, and cyclic frequency parameters, called alpha cross ambiguity function (alphaCAF), has been developed to exploit signal modulations with cyclostationary properties. By exploiting cyclostationarity, alphaCAF can produce separate unbiased TDOA and FDOA estimates that will in turn yield reliable geolocation estimates for precision emitter location applications even when severe interference causes conventional methods to fail. In this thesis the alphaCAF parameter estimation (TDOA, FDOA, Cyclic Frequency) algorithm is introduced along with a complete analysis of its performance compared to conventional estimators. A connection is also made between the alphaCAF algorithm and the additional steps needed to perform an emitter location technique.

Applying Machine Learning to Enterprise Alert Management
The network infrastructure for an enterprise system consists of many servers and hardware. Most modern day electronics are far from perfect and failures are common within a huge network. Enterprise systems records alerts (i.e. errors, failures, warnings, etc.) from the network into a database. These alerts in enterprise systems are growing in complexity and magnitude. The massive amounts of alerts reported are far too large to be managed by humans and usually only a subset is inspected. This project consists of three parts: first we performed an exploratory analysis of enterprise alert data to see if patterns existed. Next we created an alert simulator based on a mixture of Markov chains. Finally we extended the raw data with temporal features and performed an analysis using machine learning algorithms in WEKA.

Enhancing WebGen5 with Access Control, AJAX Support, and Editable-and-Insertable Select Form
WebGen is a software tool for generating Web scripts automatically for a Web-based database application. In this project, access control, AJAX support, and editable-and-insertable table mechanisms were added to WebGen. With our access control mechanism, an access-control level can be specified for each table. In access control level 1, for example, a user can read any records, and a logged-in user can insert records and update and delete the records inserted by her.

There are five access control levels. WebGen now can generate an AJAX server-side PHP script that retrieves, based on a given value, one or multiple records from the database. The given value may be selected from a dropdown list in a form, and the retrieved value or values can be set in an input element or in a select element as options, respectively.

With an editable-and-insertable select form, a user can now read, insert, update, and delete multiple records in a table at one time.

Correlated Level Shifting
Correlated level shifting (CLS) is introduced as a technique to provide true rail-to-rail performance while simultaneously reducing errors from finite op-amp gain. CLS is a technique similar to output referred correlated double sampling, except the sampling process stores the signal on a capacitor instead of the error. There is no speed penalty. CLS is applied to a 20M Sample/S, 11mW (analog) pipelined A/D converter which achieves 10.5 ENOB operating 16mV from rails using an op-amp with 30dB loop gain and 0.9V supply. Future research directions will also be discussed.

Interface effects in oxide based thin-film transistors
The goal of this research is to study the effect of different dielectric materials at the channel-gate dielectric interface of oxide based thin-film transistors. Oxide based thin-film transistors provide a feasible route towards large-scale electronics, flexible electronics and transparent electronics due to high performance at plastic compatible processing temperatures. Materials used for oxide based electronics and figures of merits will be discussed.

Finding and Using Chokepoints in Stratagus
This paper describes a method for finding areas of interest on a two-dimensional grid map used in the real-time strategy engine Stratagus. The method involves discovering chokepoints where through all simulation agents must pass. Using a set of tunable parameters, a full set of chokepoints are located. The redundant and useless chokepoints are then filtered out of the set. The resulting chokepoints can then be used to create a graph of the high-level map structure. The method used to cull less-useful chokepoints is presented. Secondarily, two algorithms were developed that help decide at which chokepoints a limited number of defensive structures may be placed for the greatest benefit. The results of a series of tests are given that show that these algorithms are valuable: tower placements based on both the optimal and greedy implementations, built on the maximum network flow of the resultant graph, perform markedly better than random placement.

Further, the framework (also by the author) used in this project is dissected.

Architecture Design of Multiplexed Incremental Analog-to-Digital Converters
Analog-to-Digital Data Converters (ADCs) used in instrumentation and measurements often require high absolute accuracy, including excellent linearity and negligible dc offset. Incremental data converters (IDCs) provide a solution for such measurement applications. Since IDCs are essentially delta-sigma (ΔΣ) converters with reset operation before each conversion, they retain most of the advantages of conventional ΔΣ converters, and yet they are capable of offset-free and accurate conversion.

Most of the previous research on incremental converters is for single-channel and dc signal applications, where they can perform extremely accurate data conversion with more than 20-bit resolution. In this thesis, the operation and the performance of IDCs in both frequency and time domain is analyzed. Design techniques for implementing multiplexed IDCs to convert narrow bandwidth ac signals are discussed too. It incorporates the operation principles, modulator topologies, digital filter design and signal-to-noise ratio optimization methodology. The theoretical analysis is verified by simulation results.

Effective Decision-Theoretic Assistance through Relational Models
Building intelligent computer assistants has been a long-cherished goal of AI. Many intelligent assistant systems were built and fine-tuned to specific application domains. In this work, we develop a general model of assistance that combines three powerful ideas: decision theory, hierarchical task models and probabilistic relational languages. We use the principles of decision theory to model the general problem of intelligent assistance. We use a combination of hierarchical task models and probabilistic relational languages to specify prior knowledge of the computer assistant. The assistant exploits its prior knowledge to infer the user's goals and takes actions to assist the user. We evaluate the decision theoretic assistance model in three different domains including a real-world domain to demonstrate its generality. We show through experiments that both the hierarchical structure of the goals and the parameter sharing facilitated by relational models significantly improves the learning speed of the agent. Finally, we present the results of deploying our relational hierarchical model in a real-world activity recognition task.

Analysis and Design Techniques for Sampling Linearity and Nano-Joule Temperature Sensing
A novel model predicts tracking nonlinearity (NL) in the form of harmonic distortion (HD) for weakly NL (i.e. SFDR>30dBc) first order open-loop sampling circuits. The mechanisms for the NL are exponential settling, amplitude modulation, phase modulation and discrete-time modulation. The model demonstrates that HD typically increases at 20 dB per decade over most standard operating ranges and is a function of input frequency, sampling bandwidth, input amplitude, the sample rate and component nonlinearity. Application of the model is reduced to the equivalent of frequency-independent nonlinearity analysis over this range, requiring only a Taylor series expansion of the NL time constant. Design insight is given for common MOS switch types, revealing a high correlation between HD and bandwidth. The first method to quantify the tradeoff between thermal noise (SNR) and linearity (SFDR) for sampling circuits is presented. Measured HD2, HD3, HD4 and HD5 versus frequency at multiple sample rates of a Sample and Hold test chip fabricated in a 0.25µm 1P5M CMOS process and Spectre simulation results support the findings. The results broadly apply to switched capacitor circuits in general and sampling circuits specifically, regardless of technology.

Passive (battery-free) wireless sensor networks present numerous design challenges, particularly energy consumption, at both the system and sensor level. Energy budgets for such a wireless sensor are orders of magnitude lower than one powered by a battery. Thus, the overriding design goal of this work is to achieve the minimum possible energy consumption for a temperature to digital converter, which consists of a temperature sensor and an analog to digital converter (ADC). Employing a ratio-metric measurement principle that eliminates the need for a reference voltage and its buffer, a temperature to digital converter design is proposed that theoretically improves upon the best energy consumption per conversion reported to date for temperature to digital converters by two orders of magnitude to roughly one nano-joule per conversion. It operates on a 1V supply and consumes 1.4µA at a 20kHz sample rate. Each seven bit conversion is achieved in 10 clock cycles using successive approximation programmable gain amplifier architecture with only a single amplifier and comparator. The proposed design has been fabricated in a 0.18µm SiGe BiCMOS process and is in the early stages of characterization.

Thin-film Inorganic Solar Cells
The primary objective of this thesis is to explore new absorber and p-type window layer materials for thin-film solar cell applications. Material investigations include iron silicon sulfide (Fe2SiS4) and barium copper tin selenide (BaSn2SnSe4) for absorber applications, and barium copper tellurium fluoride (BaCuTeF) for p-type window layer applications. Experiments involving the insertion of BCTF window layers into cadmium telluride (CdTe) and copper indium gallium diselenide (CIGS) thin-film solar cells is elucidated via interface assessment using modern Schottky barrier and heterojunction theory. The experimental work performed benefits from the availability of a new custom designed electron beam thin-film deposition system. Assistance in the construction and installation of this tool in the design of a load lock and the development and implementation of an operating procedure for this tool are described.

Permanent Magnet Helical Screw Drive
Engineering solutions for linear to rotary conversion and rotary to linear conversion typically rely on the use of mechanical devices to convert linear thrust to rotating torque and visa vi. These conventional conversion methods require lubrication, have wear surfaces exposed to high loading, require preventative maintenance, and require periodic replacement of worn components. Friction, mechanical wear, and lost efficiency are a consequence of using such conversion systems. Such limitations can be overcome by replacing the mechanical thrust converting elements with permanent magnetic forces. This thesis explores the replacement of a screw-nut thread engagement with permanent magnet threads. By replacing the frictional elements (threads) of a ball screw system (for example) with permanent magnets, it is conceivable that a highly reliable and efficient linear to rotary system can be employed.

Such a system will be explored for the purpose of ocean wave energy conversion but may be extended to other applications. Models using analytic calculations, finite element analysis, and physical experiments are explored to investigate the feasibility of such a system. Full scale applications and system integration to wave energy converter buoys are important considerations for such a device and these aspects of system design will also be explored.

Continuous Time Input ADCs
Analog-to-digital converters (ADCs) convert analog signals into digital format. Processing signals in digital format has become cheaper as digital circuits shrink in size. This has led to widespread availability of mobile devices from ipods to cell phones.

Some applications demand higher performance ADCs-posing a real challenge for I.C. designers. Such applications are cell phone base-stations and medical imaging. When designing such devices, designers strive to add as little noise and as little distortion as possible to the signal.
This becomes increasingly more difficult at higher sampling rates and higher signal bandwidths. Oftentimes such devices consume considerable power -ruling out battery powered applications.

Continuous time input Pipelined ADCs solve a number of challenges present in state-of-the-art ADCs:

1. High performance pipeline ADCs burn a lot of power due to op-amp requirements 2. Sampling distortion 3. Bootstrap switches are required for good distortion 4. High performance pipeline ADCs occupy significant silicon area 5. Limited input voltage range 6. Driving pipeline ADCs from the outside world is difficult 7. An anti-alias filter is typically required in front of the ADC

Such an ADC is composed of a continuous time front end that resolves some bits in the continuous time domain followed by a conventional back-end pipeline ADC. The key aspect of the continuous time front end is a circuit that estimates the signal ahead of time. This enables a continuous time ADC front end that is power efficient and eases the challenges listed above.

An automated web crawl methodology to analyze the online privacy landscape
Protecting end-users privacy and building trust are the two most important factors needed to support the growth of ecommerce. The increased dependence on the Internet for a wide variety of daily transactions causes a corresponding loss in privacy for many users, as virtually all websites collect data from users directly or indirectly while performing business with them.

In this thesis I have used a web crawler named “iWatch” which serves as an instrument to collect basic statistics on the state of privacy, security, and data-collection practices on the web. I have looked at several interesting practices, and ways of examining the data. This thesis is also meant to serve as a point for reflection and discussion about which practices to observe, and how the raw data from such a system can and should be evolved and made available to a wider audience.

The purpose of this thesis is to show web-crawling is a valid approach to mass data collection over the internet with the aim of predicting privacy practices and analyzing how they have evolved in the last three years in terms of geography, legislation, risks, biases and flows.

Finally I demonstrate methods to show how to control bias while collecting data, and I propose a probabilistic mathematical model to limit the depth of search to achieve wider breadth for web crawling techniques in the future.

A Probabilistic Model for Anomaly Detection in Remote Sensor Streams
Remote sensors are becoming the standard for observing and recording ecological data in the field. Such sensors can record data at fine temporal resolutions, and they can operate under extreme conditions prohibitive to human access. Unfortunately, sensor data streams exhibit many kinds of errors ranging from corrupt communications to partial or total sensor failures. This means that the raw data stream must be cleaned before it can be used by domain scientists. In our application environment-the H.J. Andrews Experimental Forest-this data cleaning is performed manually. This thesis introduces a Dynamic Bayesian Network model for analyzing sensor observations and distinguishing sensor failures from valid data for the case of air temperature measured at a 15-minute time resolution. The model combines an accurate distribution of seasonal, long-term trends and temporally localized, short-term temperature variations with a single generalized fault model.

Experiments with historical data show that the precision and recall of the method is comparable to that of the domain expert.

The Commentator Information System: understanding journalists' needs to overcome cognitive load and navigation issues
Nowadays, sports events are a significant part of the every-day entertainment with local, national, and international championships. A lot of money is invested by broadcasting companies to attract new and more viewers, acquire broadcasting rights, or send entire crews on site to cover such events. Journalists are among the few who go on site. To perform their job and make appealing live commentaries, journalists need a lot of information about athletes, past and live results, records, etc. The Commentator Information System (CIS) is the on-site tool used by journalists for these purposes, and made available by the organizers.

The CIS is an LCD touch-screen device that allows users to retrieve sports data by selecting specific buttons on the interface: final or heat results, intermediate times, weather conditions, medal standings, etc. There is one CIS per event; hence the system can cover dozens of different disciplines (e.g. during the Olympic Games) at the same time.

There has been research conducted on how to improve TV and online viewers’ experience during sports events but nothing, as of today, about improving journalists’ work environment. Moreover, their work conditions are very stressful; if they make mistakes in their statements, it can have negative consequences on their career. Thus, the CIS has to be reliable from both a system and usability perspective.

Through this study I found important navigation issues and some missing information concerns. I observed that journalists rely heavily on their own notes and not much on the CIS. I discovered, users do make mistakes and have difficulties multitasking under this type of pressure. Finally, I noticed some gender differences in the task performances when users have to find information in the CIS.

Gender differences in end-user debugging strategies
There has been little prior research reporting strategy usage in end-user problem solving, and even lesser using gender as a factor. Without this type of information, end-user programming systems cannot know the “target” at which to aim, if they are to support male and female end-user programmers’ debugging. As a background to the thesis, an experiment was conducted by our group members, where the participants were given a post session questionnaire that had an open-ended question about what debugging strategies they adopted in finding and fixing errors. It was found that among the mentioned strategies, testing and code inspection had significant statistical differences among male and/or female success groups. This thesis’s goal is the investigation of the behavioral evidence of the two primary strategies, testing and code-inspection using gender as a factor. Using quantitative and qualitative methods, we analyzed the two strategies reported, and looked for relationships among participants’ strategy choices, gender, and debugging success. Our results indicate that males and females debug in quite different ways, and the debugging strategies that worked well for the males were not the same ones that worked well for the females. Our results also reveal that tools currently available to end-user debuggers may be especially deficient in supporting debugging strategies used by females.

At frequencies exceeding 1-2 GHz, the reactive nature of a silicon substrate must be accounted in the substrate network models used in substrate coupling simulation. High-frequency substrate models, containing reactive components, must be validated through high-frequency network analyzer measurements.

Prior fabricated test fixtures have been modified to enable high-frequency (up to 20 GHz) network parameter measurements of a 0.35 µm CMOS heavily-doped silicon substrate through an off-chip probing scheme. The performance of the test fixture and the measurement deembedding procedure has been evaluated, and suggestions for future improvements are presented.

New probing scheme is proposed to enable high-frequency network parameter measurements of a silicon substrate. The design of the test structures and the deembedding procedure has been validated through extensive simulations in HFSS.

Explaining Debugging Strategies to End-User Programmers
There has been little research into how end-user programming environments can provide explanations that could fill a critical information gap for end-user debuggers – help with debugging strategy. To address this need, we designed and prototyped a video-based approach for explaining debugging strategy, and accompanied it with a text-only approach. We then conducted a qualitative empirical study with end-user debuggers. The results reveal the influences of the explanations on end-user debuggers’ decision making, how users reacted to the video versus textual media, and the information gaps the explanations closed. The results also reveal issues of particular importance to explanations of this type.

Low-Complexity High-speed VLSI Design of Low-Density Parity-Check Decoders
Low-Density Parity-check (LDPC) codes have attracted considerable attention due to their capacity approaching performance over AWGN channel and highly parallelizable decoding scheme. They have been considered in a variety of industry standards for the next generation communication systems. In general, LDPC codes achieve outstanding performance with large codeword lengths (e.g., N>1000 bits), which lead to a linear increase of the size of memory for storing all the soft messages in LDPC decoding. In the next generation communication systems, the target data rates range from a few hundred Mbit/sec to several Gbit/sec. To achieve those very high decoding throughput, a large amount of computation units are required, which will significantly increase the hardware cost and power consumption of LDPC decoders. LDPC codes are decoded using iterative decoding algorithms. The decoding latency and power consumption are linearly proportional to the number of decoding iterations. A decoding approach with fast converge speed is highly desired in practice.

This thesis considers various VLSI design issues of LDPC decoder and develops efficient approaches for reducing memory requirement, low complexity implementation, and high speed decoding of LDPC codes. We propose a memory efficient partially parallel decoder architecture suited for quasi-cyclic LDPC (QC-LDPC) codes using Min-Sum decoding algorithm. We develop an efficient architecture for general permutation matrix based LDPC codes. We have explored various approaches to linearly increase the decoding throughput with a small amount of hardware overhead. We develop a multi-Gbit/sec LDPC decoder architecture for QC-LDPC codes and prototype an enhanced partially parallel decoder architecture for a Euclidian geometry (EG) based LDPC code on FPGA technology. We propose an early stopping scheme and an extended layered decoding method to reduce the number of decoding iterations for undecodable and decodable sequence received from channel. We also propose a low-complexity optimized 2-bit decoding approach which requires comparable implementation complexity to weighted bit flipping (WBF) based algorithm but has much better decoding performance and faster converge speed.

Modified VLSI Designs for Error Correction Codes
Nowadays, error correction codes have become one integral part in almost all the modern digital communication and storage systems. With the continuously increasing demands for higher speed and lower power communication systems, efficient VLSI implementations of those error correction codes have great importance for practical applications. In this thesis, several VLSI design issues for Viterbi decoder and Low-Density Parity-check (LDPC) decoder will be discussed. We propose a low-Power memory-efficient Viterbi decoder to reduce the memory read operations in the survivor memory unit (SMU) and the memory size of SMU. We develop a parallel Viterbi decoder for high throughput applications. We also propose an efficient early stopping scheme to reduce the number of decoding iterations for LDPC codes decoding.

Network Coding in Relay Networks
Transmission over wireless networks presents multiple technical challenges due to noise, interference, fading, power constraints, and bandwidth limitation, among others. Different solutions have been proposed to overcome these issues and some of them are treated here. Cooperative diversity has been proposed as an implementation for networks where terminals are restricted to using physical arrays; this technique implements space diversity by creating virtual antennas arrays with cooperating nodes in order to combat multipath fading. Recently, network coding has been presented as a technique to increase the throughput in multicast networks. Most of the work done on the topic considers an error free transmission and very few works have taken into account the errors due to the nature of the wireless channel. This thesis proposes the use of network coding over some scenarios in relay networks, in order to obtain diversity. It also addresses some cooperative protocols and their performance in terms of bit error rate. Moreover, reliability criteria based on channel information are established for a practical network implementation. In short, we propose a scheme for a wireless network using ideas based on network coding.

Structured Gradient Boosting
The goal of many machine learning problems can be formalized as the creation of a function that can properly classify a given input vector. While this formalism has produced a number of success stories, there are notable situations in which it fails. One such situation arises when the class labels are composed of multiple variables, each of which may be correlated with all or part of the input or output vectors. Such problems, known as structured prediction problems, are common in the fields of information retrieval, computational linguistics, and computer vision, among others. In this dissertation, I will discuss structured prediction problems and some of the previous approaches to solving them. I will then present a new algorithm that combines strong points of previous approaches while retaining their generality. Finally, I will show a number of novel ways in which this algorithm can be applied effectively, highlighting applications in learning by demonstration and music information retrieval.

Simulation and Modeling of Substrate Noise Generation from Synchronous and Asynchronous Digital Logic Circuits
Efficient methods for simulating the substrate noise generated by complex synchronous and asynchronous digital logic circuits are presented. By simulating digital logic at the gate level, and precharacterizing the gates, the substrate noise generation can be predicted and used in a transistor level simulation of the sensitive analog blocks. This approach is shown to be accurate for both traditional CMOS logic and NULL Convention logic (NCL) by correctly modeling critical gate characteristics. Synchronous and asynchronous versions of a pseudo-random number generator (PRNG) are implemented in a 0.25 µm CMOS test chip. Simulations validate both a standard transistor level setup and the improved new predictive substrate noise approach against measurements. Simulations with different implementations of an 8051 processor core are in good agreement with measurements from another 0.25 µm CMOS test chip, and show validation with a large and complex circuit.

Development of Oxide Semiconductors: Materials, Devices, and Integration
The aim of this dissertation is to develop oxide semiconductors by radio-frequency sputtering for thin-film transistor (TFT) applications. A variety of oxide semiconductors are used as the TFT channel layer, including indium gallium oxide (IGO), zinc tin oxide (ZTO), and indium gallium zinc oxide (IGZO). The variety of materials used underscores the abundance of materials options available within this nascent technology, with each material exhibiting unique chemical, mechanical, and electrical properties. The influence of several deposition parameters is explored; oxygen partial pressure of the deposition ambient is found to have a profound effect on the electrical characteristics of each material. With optimized deposition conditions, TFTs based on these materials exhibit excellent electrical properties, even when annealed at low-temperature (175 °C). Specifically, ZTO-based TFTs which are subjected to a 175 °C post-deposition anneal exhibit a channel mobility near 9 cm2V-1s-1. However, advancement of this technology also requires research in integration-related issues. Therefore, the effect of channel layer passivation and of TFT stability is evaluated. Passivation of the oxide semiconductor surface is required for circuits which employ multiple levels of interconnect and for mechanical/chemical protection of devices. Here, successful passivation of IGO, ZTO, and IGZO-based TFTs is demonstrated using SU-8, a negative tone epoxy-based photoresist. To appraise TFT stability, a constant voltage bias stress test of 1000 minutes is utilized, where the drain current, ID, is monitored throughout the duration of testing and the turn-on voltage, Von, is evaluated before and after stressing. TFT stability is found to be correlated to the turn-on voltage of a device and to the thickness of the semiconductor layer. IGZO-based TFTs with excellent stability are demonstrated, exhibiting almost no decrease in ID or any shift in Von throughout the duration of bias stress testing.

Sustainable Power Management of Microelectronics
Even though renewable energy sources have been integrated for high power utilities in Mega-Watts(MW) and very low power applications in milli-Watts(mW) domain, there is very limited work in this area for commonly available mobile computer systems operating with a total average power range of few Watts to tens of Watts. A holistic approach is proposed in this research by investigating renewable energy sources and the associated power electronics for the low power mobile computing market, including Portable, Ultra-Portable, and Mini-Portable form factors. Both thermoelectric (TE) and photovoltaic (PV) energy extraction techniques and materials are explored with the goal of achieving best sustainability.

New metrics were defined for proper evaluation of new technologies instead of the traditional industry metrics, like MHz, which focuses on only one aspect of the problem. Semi-realistic workloads have been assumed for fair treatment of dynamism of microelectronic components and of maximum energy available in the system, unlike the previously published work in the area which assumed unrealistic constant heat sources. A Thermoelectric System Solver ("TESS") has been developed, and was used to simulate the application of TEs for improved sustainability of different platform types under three different schemes: Parallel TE Generation (PTG), Series TE Generation (STG), and Hybrid TE Conversion (HTC). A platform approach has been taken by including chipset, unlike previous work, which included only CPU to the TE analysis. Photovoltaic Power Generation (PPG) has been added to the energy scavenging system under realistic user conditions. Simple prototypes for HTC and PPG schemes have been individually tested and characterized to quantify the range of electrical parameters.

In the last phase of the research, new power architecture and power electronics design approaches were studied in order to store the extracted energy from multiple sources to the existing system battery. The feasibility of operating the power electronics at realistically low power levels obtained from previous experiments has been projected through simulation and measurement data using off-the shelf components.

Thin-Film Transistors with Amorphous Oxide Channel Layers
In recent years, a new class of high-performance thin-film transistors (TFTs) has emerged comprising amorphous oxide channel materials composed of heavy-metal cations (HMCs) with (n-1)d10ns0 (n ≥ 4, where ‘n’ refers to the row of the periodic table) electronic configuration. This thesis is devoted to the fabrication and characterization of TFTs employing two such amorphous oxide channels: zinc indium tin oxide (ZITO) and zinc tin oxide (ZTO).

ZITO is demonstrated as a transparent and amorphous quaternary channel material for TFTs. Optical transmission of ZITO channels is ~ 85% in the visible portion of the electromagnetic spectrum (~ 400 to 700 nm). Peak incremental mobilities of 5 – 19 cm2V-1s-1 and turn-on voltages of -4 to -17 V are obtained for TFTs post-deposition annealed at 100 – 300 °C, respectively. Current-voltage measurements indicate n-channel, depletion-mode transistor operation with excellent drain current saturation, and a drain current on-to-off ratio greater than 106.

Additionally, two routes are explored to successfully fabricate enhancement-mode TFTs employing ZTO as the channel layer. Initially, Ba is added to the ZTO material system to obtain BZTO, a low cost quaternary amorphous material system similar to indium gallium zinc oxide. BZTO TFTs are enhancement-mode devices with positive near-zero turn-on voltages and BZTO channels remain amorphous at anneal temperatures as high as 700 – 800°C. However, the incremental mobilities of these devices are less than 5 cm2V-1s-1. Thus, Ba doping is found to be an unsuitable route for enhancement-mode TFT development. Subsequently, an experimental effort is undertaken to optimize the ZTO process for the 1:1 ZnO:SnO2 stoichiometry. Primarily, the ambient O2 partial pressure during channel deposition and the post-deposition annealing temperature are deduced to be the two primary processing parameters most significantly impacting TFT performance. Enhancement-mode TFTs are demonstrated for O2 partial pressure percentages ≤ 5% of the ambient Ar/O2 processing pressure and annealing temperatures of 300 – 600°C. The best devices realized exhibit incremental mobilities of 10 – 30 cm2V-1s-1 and turn-on voltages of 0 – 5 V.

Image Feature Detection and Matching for Biological Object Recognition
Image feature detection and matching are two critical processes for many computer vision tasks. Currently, intensity-based local interest region detectors and local feature-based matching methods are used widely in computer vision applications. But in some applications, such as biological object recognition tasks, within-class changes in pose, lighting, color, and texture can cause considerable variation of local intensity. Consequently, object recognition systems based on intensity-based interest region detectors often fail. This dissertation proposes a new structure-based local interest region detector called principal curvature-based region detector (PCBR) that detects stable watershed regions within the multi-scale principal curvature images. This detector typically detects distinctive patterns distributed evenly on the objects and it shows significant robustness to local intensity perturbation and intra-class variation. Second, this thesis develops a local feature matching algorithm that augments the SIFT descriptor with a global context feature vector containing curvilinear shape information from a much larger neighborhood to resolve ambiguity in matching. Moreover, this thesis further improves the matching method to make it robust to occlusion, clutter, and non-rigid transformation by defining affine-invariant log-polar elliptical context and employing a reinforcement matching scheme. Results show that our new detector and matching algorithms improve recognition accuracy and are well suited for biological object recognition tasks.

Supply Noise Suppression in Phase Locked Loops
Supply noise is major performance limiting factor in all phase-locked loops. This work utilizes a low-drop out regulator and the noise-free control voltage of the VCO and generates a clean power supply to all the building blocks. Simulation results indicate that the proposed technique reduces the supply-noise induced jitter from 60ps to about 2ps.

A theoretic treatment of maintenance
Professional programmers have more tools and information at their disposal than ever before, and yet maintenance still requires much effort. What information in programs, bug reports, and other artifacts are we not currently using? I propose to investigate this question.

I plan to examine what information programmers use to comprehend programs and navigate within programs, as well as the information they use in bug reports and other artifacts as they engage in maintenance.

From this research, I expect to develop a theoretical understanding of human aspects of maintenance sufficient to predict programmer behavior and their needs for, use of, and loss of information. Ultimately, this research will provide a theoretical (not ad-hoc) basis for the evaluation and development of new maintenance tools.

Complex Patterns in Gender HCI: A Data Mining Study of Factors Leading To End-User Debugging Success for Females and Males
Most of the work so far in the subfield of Gender HCI has followed a theory-driven approach. Established theories, however, do not take into account specific issues that arise in end-user debugging. We suspected that there may be important information that we were overlooking. We therefore employed a methodology change: turning to data mining techniques to find hidden patterns and relationships in females' and males' feature usage patterns. This thesis reports two data mining studies to help discover complex ties among static, dynamic, and success data collected in end-user debugging sessions. Study 1 was our first step, and was used to derive new hypotheses about females' and males' strategies and behaviors. In Study 2, we then applied different data mining algorithms to a larger data set to describe, summarize, segment, and detect interesting patterns. We found that most of the factors that tied with females' success in debugging were different than those that tied with males' success in debugging and vice versa. The results will ultimately help Gender HCI researchers better support end-user debuggers of both genders.

Accuracy Versus Cost in Distributed Data Mining
A basic tradeoff to consider when designing a distributed data-mining framework is the need for a compromise between the cost of communication and computation resources and the accuracy of the mining results. This is essentially a decision of whether it is more efficient to communicate all of the data to a central site for analysis, possibly increasing the accuracy of the results, or is it more efficient to mine the data locally at each of the remote sites and then combine the results, possibly reducing the use of communication and computation resources. This research attempts the design, analysis, and implementation of an efficient distributed and cumulative learning algorithm with performance guarantees that are provable relative to its centralized or batch counterparts for knowledge acquisition from distributed data sources that will address this tradeoff.

This thesis also develops a methodical mathematical framework to describe this type of tradeoff, describes the reduction of the problem to a constrained optimization problem, and demonstrates techniques to balance cost and accuracy levels.

A SAT-based Planning Framework for Optimizing Resource Production
Domain-independent automated planning is concerned with computing a sequence of actions that can transform an initial state into a desired goal state. Resource production domains form an interesting class of such problems, in that they typically require reasoning about concurrent durative-actions with continuous effects while minimizing some cost function. Although formulating planning problems as instances of SAT has proven to be very successful within the realm of STRIPS planning problems, where states and time are discrete and actions are instantaneous, it is unclear whether the same success can be transferred to resource production. Some of the major drawbacks to these systems are that they do not support reasoning about metric quantities, continuous time, and cost functions. TM-LPSAT was one of the first successful systems to reason about both metric quantities and continuous time within a SAT framework. However, TM-LPSAT does not provide a way to reason about cost functions. In this thesis we extend the framework in a way that allows it to be capable of minimizing the costs, in our case makespans, of the plans that it finds.

Novel Control of Ocean Wave Energy Converter
Ocean wave energy is rapidly becoming a field of great interest in the world of renewable energy. Significant advancements in the design and technology are being made to make wave energy a viable alternative for our energy demands. The two major hurdles for ocean wave energy to make a significant contribution to our nations energy needs are the permitting of commercial wave parks and the creating an ocean wave energy converter that is cost effective and reliable. Significant improvements in wave energy converters can be made with the implementation of specialized generators and power electronic technologies. This will allow for dynamic generator loading that will give the ability to control the buoy in order to increase power production and reliability. This text discusses the development of a novel control design for a wave energy generator that focuses on reliability and power production.

Using Webservices for Image Processing in a Desktop Widgets Engine
Desktop widget engines have emerged as an alternative for completing simple tasks without the need for a full-blown application or constant user interaction. Widgets can simply display data in a compact and visually appealing manner (such as stock tickers, weather forecasts, and news notifications), or go so far as to provide alternative interfaces to sites that expose their services via an API.

This project aims to develop a graphics application where the key features are provided neither locally nor by a single host. The Yahoo! Widgets engine is used to design a simple image processing interface where processing operations are mapped to widgets that can be connected together to create more complex operations. Actual data processing occurs remotely via calls to a REST-style Java webservice to allow for a non-local and decentralized system.

Novel Control of a Permanent Magnet Linear Generator for Ocean Wave Energy Applications
Wave energy conversion devices are a rapidly growing interest worldwide for the potential to harness a sustainable and renewable energy source. Due to the oscillatory nature of ocean waves, the power generated from a permanent magnet linear generator (PMLG) for ocean wave energy conversion is pulsed. Focusing on direct drive technology, the PMLG directly translates the motion of the waves into energy. The power generated, left unconditioned, is not easily usable or stored.

With conventional diode rectification topologies, line currents can not be controlled easily, resulting in an uncontrolled generator output and force. With an active rectifier topology, the real and reactive power from the PMLG is fully controllable. This thesis will investigate the generator modeling and design of a novel three-phase active rectifier topology and force controller with a dc-dc converter for bus voltage regulation. An in depth analysis for the controller design and simulations are presenting. Hardware for the three-phase active rectifier is specified and built with lab testing. The controller design is implemented with National Instruments' LabView and compiled on a CompactRIO real-time controller.

Investigating XNA as a General Purpose Visualization System
Microsoft's recent release of the XNA framework, successor to managed DirectX, targets hobbyists and smaller developers, but it also provides a convenient platform for scientific visualization. It offers easy access to modern video card's shader capabilities, supplies useful math and geometry libraries, and eliminates much of the boilerplate code so common in graphics applications.

This project's purpose was to investigate the functionality of the new framework, contrast it with the typical OpenGL/C++ combination, and evaluate it's difficulty for learning graphics. Testing the framework's capabilities involved porting homework assignments from OSU's scientific visualization and shaders classes. A sacrifice in CPU efficiency was expected from using C#/CLR 2.0 rather than precompiled code, but considering that most visualization-heavy applications are GPU bound anyway, the shortened development time up is a tempting advantage.

Scientific Visualization in Dense Forest Environments
Over the last decade, there has been an advancement in the use of visualization research in other disciplines. The impact of visualization can be seen in fields such as medical, architectural, mathematics, and many other fields. However, visualization in dense forest environments has been inaccessible in many cases to scientists. In this talk, a watershed in the HJ Andrews experimental forest will be used as a case study to investigate various visualization options available to scientists. Both analog and digital visualization techniques will be explored as ways to better understand the surrounding environment. For example, the analog visualization of bubbles "flowing" along the air stream within the watershed can be digitally captured through stereo imagery. As digital model of this flow could then be constructed. In addition, data integration from various sensors along with modeling of the watershed will be explored as methods for scientific understanding. Ultimately, these techniques will be explored in order to visualize the forest in ways that scientists had not imagined.

CAM: A New Circuit Augmentation Method for Modeling Interconnects and Passive Components
Contemporary circuit design involves significant computer-based simulation, calling for a balance between circuit model accuracy and simulation run time. Traditionally, circuit modelers concentrated on producing either (1) physically-based models, where each element in the model correlates to a physically meaningful aspect of the device being modeled or (2) mathematically-based "macromodels," designed to be efficient to simulate without ties to the device’s physical underpinnings. While each approach has significant value, the strengths of one are often the weaknesses of the other.

This work presents CAM, the Circuit Augmentation Method, that integrates some of the best aspects of each approach. Based on the assumption that high-accuracy, multi-port simulation or measurement data for the device under consideration is available, the methodology augments an existing, user-provided equivalent circuit model that is reasonably accurate over some frequency band with discrepancies elsewhere. Macromodels using rational polynomials are derived via standard least-squares or vector fittings approaches and are logically "added" to the user model creating a result that is potentially both fast to simulate yet still physically meaningful. An important aspect of CAM is its perturbational nature: It is shown that perturbation of the user model’s component values (or similar attributes) is necessary for optimal results.

CAM is a general-purpose technique that is applicable to the often difficult problems of modeling circuits requiring wideband accuracy or those incorporating highly-distributed structures. This utility is demonstrated over several two-port examples, including a broadband oscilloscope probe tip, a spiral inductor on a lossy silicon substrate, and a highly-distributed and lossy test circuit.

A Practical Implementation of Self-efficacy Theory to Improve the Engineering Curriculum
What are the most effective ways to improve the engineering curriculum? Improvements should result in increased student retention, undergraduates who are more industry-ready and graduates who are better prepared to be leaders. Current research suggests that the best predictor of persistence is a person’s self-efficacy. The focus of this thesis is a practical application of the theory of self-efficacy in an integrated effort to improve the engineering curriculum.

The EECS department has already been making an effort to improve the undergraduate educational experience via the introduction of the TekBots program in labs. Labs should be designed and implemented in such a way that the undergraduates have a beneficial experience which may increase their self-efficacy and hence, likelihood to persist in the engineering program as well as better prepare them for industry. A redesign, implementation and evaluation of integration of the TekBots program into a junior-level course, Electronics II (ECE 323), is presented.

Another important factor in improving retention is by providing undergraduates with role models who model success and give encouragement. TAs are prime candidates to be mentors. Also, graduate students are expected to be leaders in many settings. One solution is to rethink the traditional philosophy behind the position of TA. Leadership training for TAs is an innovative and efficient solution because it encompasses more than simple teaching techniques and draws on other disciplines. A design, implementation and evaluation of a leadership training course for TAs is presented.

Layer 2 handoff solution in mobile device
This paper proposes a technique called Global Path-Cache (GPC) that provides fast handoffs in WLANs. GPC maintains a history of mobile stations' mobility patterns in a network to assist in the prediction of the next point-of-attachment. GPC properly captures the dynamic behavior of the network and MSs, and provides accurate next AP predictions. Our simulation study shows that GPC virtually eliminates the need to scan for APs during handoffs and results in much better overall handoff delay compared to existing methods.

A Linear Test Bed for Characterizing the Performance of Ocean Wave Energy Converters
Determining the performance characteristics of various ocean wave energy converters (OWEC) has proven to be difficult due to problems replicating a baseline motion profile in the ocean or wave tank to compare these devices. The linear test bed seeks to mechanically simulate the relative linear motion between the active components experienced by a point absorber OWEC in an ocean environment. A gimbal mount allows the “float” of a point absorber OWEC to be mounted to the machine’s carriage, which is mechanically driven by timing belts. The “spar” portion of the OWEC is mounted to the base of the linear test bed so that as the carriage moves the float vertically, there is relative linear motion between the float and spar. The current control system allows researchers to input a vertical position versus time function to be tracked by the linear test bed.

However, researchers have desired to improve the linear test bed control system by implementing a force control algorithm based on hydrodynamic equations to accurately reproduce the driving force of the ocean wave. With only position control, the linear test bed will use any necessary force to follow that profile, exaggerating the capabilities of the wave especially if the device is electrically loaded. In addition, the hydrodynamic interaction of the OWEC and an ocean wave cannot be reproduced using only a position feedback control system. The linear test bed design, position control system, and a comprehensive presentation of the novel force control system are provided through this thesis work.

Gray Codes and their Applications
A n - bit Gray code is an ordered set of all 2n binary strings of length n. The special property of this listing is that Hamming distance between consecutive vectors is exactly 1. If the last and first codeword also have a Hamming distance 1 then the code is said to be cyclic.

Over the last 4-5 decades binary Gray codes have found applications in diverse areas: VLSI testing, signal encoding, ordering of documents on the shelves, data compression, statistics, graphics and image processing, processor allocation in the hypercube, hashing, computing the permanent, information retrieval, puzzles such as the chinese rings and towers of Hanoi, designing efficient combinatorial algorithms, etc. A large number of Gray code related patents in diverse areas have been granted in the last three decades and almost all of them are, in one way or another, based on the original reflected Gray code ideas.

This thesis addresses problems dealing with the design and applications of new and existing types of both binary and non-binary Gray codes. It is shown how properties of certain Gray codes can be used to solve problems arising in different domains. Design of new types of Gray codes to solve specific types of problems is also shown. We show construction of Gray codes over higher integral radices and their applications. Applications of new classes of Gray codes defined over residue classes of Gaussian integers are also shown. We also propose new classes of binary Gray codes and prove some important properties of these codes.

Sphere Decoder for MIMO Systems
Multiple-input multiple-output (MIMO) communication systems have recently been considered as one of the most significant technology breakthroughs for modern wireless communications, due to the higher spectral efficiency and improved link reliability they can provide. The sphere decoding algorithm (SDA) has been widely used for maximum likelihood (ML) detection in MIMO systems. However, the current SDA is very complex for hardware implementation, and the throughput of current SDA design is below the requirement of next generation high-speed wireless communications. Therefore, it is much desired to develop low-complexity and high-speed VLSI architecture for the MIMO sphere decoders. This research proposal is focused on the low-complexity and high-speed sphere decoder design which can achieve the ML detection for the MIMO systems. It includes the algorithms simplification, and transformations, hardware optimization and achitecture development. In this article, the principles of the proposed topics are introduced concisely; followed by current experimental results showing the applicability of some methods. A rough work plan is given in the end which will be the guideline of my Ph.D. study.

Designing and Understanding Information Retrieval Systems using Collaborative Filtering in an Academic Library Environment
Accessing information on the Web has become ingrained into our daily lives, and we seek information from many different sources, including conference and journal publications, personal web pages, and others.

Increasingly, web-based information retrieval systems such as web-based search engines, library on-line catalog systems, and subscription-based federated search systems are made available to provide an interface to collections of information from these sources. Because the quantity of new information available every day exceeds how much information individuals can handle effectively, we spend significant effort in locating information, often unsuccessfully.

This dissertation consists of three scholarly articles presenting a broad set of results with the goal of helping people find interesting information in large web document collections. The results cover three specific challenges: designing and utilizing Web document recommendation systems based on human judgment, improving recommendations based on users' web usage as a source of implicit relevance feedback data, and understanding and designing metasearch systems for academic materials. To address these challenges, a combination of offline analysis and user testing is used.

Natural Language Date-Time Parsing in Chandler™
The increasing need to share and synchronize personal information, such as schedules, tasks, emails and events, amongst users has lead to the development of inter-personal information management software like Chandler™. Chandler is being developed in Python at the Open Source Applications Foundation, San Francisco. Before I started working on the project ‘Natural Language Date-Time Parsing’, Chandler recognized only one date format, mm-dd-yy, and one time format, hh:mm AM/PM. My goal was to increase the usability and functionality of Chandler by allowing users to enter any natural language date/time formats, such as ‘May 10, 2007’, ‘3pm’ and ‘lunch tomorrow’, instead of being bound by any specific format. The project was divided into three parts. In the first project, I implemented natural language date/time parsing in the start date/time and end date/time fields for the Calendar Events in Chandler. The second project was to identify the start date/time and end date/time attributes of an Item when it is added to the Calendar. The third project involved the text widget in Chandler’s Toolbar that was used only as a search-box. I converted this text widget into a Command Line Interface(CLI) that can not only be used to search Items but also to create new Items quickly. The new Items created using CLI, were parsed for natural language date/time information to set their attributes properly.

LDMOS Transistor and Its Failure Modes
High voltage Lateral Double diffused MOS transistor (LDMOS) is typically created as an extension of the existing CMOS technology. With the breakdown voltage in the range of 20V to 150V, LDMOS transistors are commonly used as the output drivers in a wide variety of applications. It is important to determine and control the LDMOS Safe Operating Area (SOA) where the device survives the high power applications and transitions between the on and off states. The fundamental mechanisms to determine the LDMOS SOA are electrical instability and thermal instability. Depending on the device size and its application, the device failure mode might be a result of an electrical instability, thermal instability or both.

Development of Oxide Semiconductors: Materials, Devices, and Integration
Oxide semiconductors have long been used in passive applications as transparent conductors. Recently, oxide semiconductors have been used to fabricate thin-film transistors (TFTs). Since the initial report, several groups have shown that oxide semiconductor-based TFTs can be fabricated near room temperature while maintaining moderate performance. Here, several topics for oxide-based TFT research are proposed, including investigation of the primary process parameters for optimization of TFT electrical properties and integration-related topics. These integration-related topics include investigation of an electrical passivation layer, two device structures, and stability of oxide semiconductor-based TFTs. Preliminary results for several of these proposed topics will be given.

Gender HCI Issues in End-User Programming
Until recently, research has not considered whether the design of end-user programming environments, such as spreadsheets, multimedia authoring languages, and CAD systems, affect males and females differently. As a result, we began investigating how the two genders are impacted by end-user programming environments and whether attention to gender differences is important in the design of software. Evidence from other domains, such as psychology and marketing, strongly suggests that females process information and problem solve in very different ways than males. This implies that without taking these differences into account in the design of end-user programming environments, the needs of half the population for whom the software is intended are potentially being ignored. In fact, some research has shown that software is unintentionally designed for males. Our research has uncovered several factors which affect males and females differently as they engage in end-user programming. The gender differences range from the effects of self-efficacy (a form of confidence) on engagement with environment features to how males and females use “tinkering” as part of their problem-solving strategy. We further investigated the effects of several environment changes on both males and females problem solving. This research is the first to both uncover what gender differences are relevant in end-user programming environments and to address how to account for these gender differences in the design of such environments.

End-user software engineering in the spreadsheet paradigm
Spreadsheets are among the most widely used end-user programming systems. Unfortunately, there is a high incidence of errors in end-user spreadsheets, and some of these errors have high impact.

In this dissertation, we describe techniques we have developed to help end users develop safer spreadsheets. As part of our research, we have examined typical software development activities like programming, testing, and debugging from an end-user software engineering perspective, and developed approaches to support them better.

To achieve this goal, we have drawn extensively from research in the areas of software engineering and programming languages to develop techniques for the following.

1) Prevention of reference, range, and type errors by generating spreadsheets from user-defined templates.

2) Detection of unit errors by carrying out automatic consistency checking of spreadsheet formulas using labels within spreadsheets.

3) Detection of faults within spreadsheets by helping end users test better using constraint-based automatic test-case generation.

4) Correction of identified faults within spreadsheet formulas using a spreadsheet debugger that exploits the user's expectations about the output of their spreadsheets.

Multi-Platform, Blind Detection, Separation and Location of Co-Channel Emitters
Many of the most widely used methods for determining the location of an emitter involve estimating the Time-Difference-of-Arrival (TDOA) and Frequency-Difference-of-Arrival (FDOA) of a signal replica arriving at two spatially separated receivers. Most traditional methods of estimating TDOA are based on the Generalized Cross Correlation (GCC) method of time delay estimation. Methods for jointly estimating both TDOA and FDOA are often based on Complex Ambiguity Function (CAF) processing. In some applications it is necessary to go beyond the capabilities of traditional GCC and CAF processing in order to accurately estimate TDOA/FDOA for an emitter of interest within a co-channel interference environment. This can be an especially difficult problem when the receivers and emitters are moving and when long integration times are required. Research into new computationally efficient methods for estimating TDOA/FDOA for emitters in a co-channel interference environment and methods for mitigating the effects of time-varying Doppler on the TDOA/FDOA estimation are needed. During this presentation new research that addresses these topics will be introduced along with a review of the most common methods that can be found in the literature.

1/f noise of GaAs resistors and Bjt from the linear diffusion equation
This research work focuses on the mechanism of 1/f noise in GaAs resistors on semi-insulating substrates and 1/f noise due to temperature fluctuations in heat conduction in bipolar transistors. The goal of this research is to generate accurate models to explain physical origin of 1/f noise in semi-insulating substrate and semiconductor devices dissipating high power.

The model is based on a distributed equivalent circuit representation of the substrate, and shows that 1/f noise is a bulk phenomena associated with high resistivity substrates. One consequence of the theory is that in this particular instance Hooge's parameter is given by a formula which has a simple physical interpretation as the ratio of two charges, the thermal charge developed across the substrate capacitance and the charge associated with ionized donors in the resistor channel.

Power dissipation at high currents and voltages in semiconductor devices results in significant heat generation and heat conduction towards the heat sink. The device temperature is only an average value and there are as a consequence of the diffusion equation for heat flow itself temperature fluctuations about this average value. It will be shown that these temperature fluctuations can result in 1/f noise at moderately low frequencies where these frequencies are determined by the physical dimensions over which the heat flows and the diffusion transit time. The results are then related to the shot noise or white noise due to the collector current allowing a determination of the 1/f noise corner frequency.

Fusing Machine Learning into Low-Level and Mid-Level Vision
Machine learning in computer vision is the process in which an artificial system autonomously acquires knowledge from training images to solve a given task. The last years have seen machine learning methods applied to and achieved great success in an increasing variety of areas in computer vision such as: image segmentation, object recognition, object tracking, object modeling, scene analysis and so on.

But a main drawback in current work is that learning is mostly restricted to the final classifier, or equivalently, high-level vision. On the other hand, learning low-level image operation and mid-level image representation have received much less attention from the research community. For example, in object recognition area, the common-used interest region detectors and descriptors are all hand-crafted; the visual dictionary or image representation is not designed to help with discrimination.

There is widely agreement that high-performance object recognition requires fusing learning into all levels of computer vision. To address this uprising need, we will mainly focus on fusing discriminative learning into four basic processes of an object recognition system: learning interest region detector, learning discriminative visual dictionary, learning high-precision classifiers that are better suited to the dictionary-based image features, and discriminative evaluation of local features. We expect to develop more problem-specific and high-performance systems for complex object recognition applications.

In this article, the principles of the proposed topics are introduced concisely; followed by primitive experimental results showing the applicability of some methods. A rough work plan is given in the end which will be the guideline of my Ph.D study.

A 25 MHz RC Oscillator with Automatic Amplitude Control through Self-Biasing
In this paper a 25 MHz sinusoidal RC oscillator is presented. The contribution of flicker noise to the phase noise spectrum is reduced by the use of opamp-based integrator delay stages in the core oscillator. In addition, Barkhausen’s criteria is exploited to accomplish selfbiasing through automatic amplitude control (AAC). The oscillator has been designed in a 0.13μm CMOS process and achieves -40dBc/Hz phase noise at an offset frequency of 100 Hz with SFDR of -70.1dBc while consuming 2.25mA on a 1.4V internally generated supply derived from an external 1.7V source.

Fast algorithms and Applications for Multi-Dimensional Least-Squares-Based Minimum Variance Spectral Estimation
The main contribution of this thesis is development and application of four very fast computation solutions for least-squares-based (LS-based) minimum variance spectral estimation (MVSE). They are (1) fast computational solution for the 1-D covariance LS-based MVSE, (2) fast computational solution for the 1-D modified covariance LS-based MVSE, (3) fast computational solution for the 2-D covariance LS-based MVSE, (4) fast computational solution for the 2-D modified covariance LS-based MVSE. The four fast computation solutions not only significantly reduce computational complexity and save memory from array to vector sizing proportionalities, but inherit improved-feature detail from the corresponding direct methods of 1-D and 2-D LS-based MVSEs. The two 2-D fast computational solutions numerically produce the same results as the corresponding 1-D fast solution when the estimation order in one of two dimension is set to zero.

LS-based MVSEs are high-resolution spectral estimation which have been interested to the sensor community (for example, radar, sonar, communication signal localization, and seismic velocity discrimination) for extracting and resolving more features from limited data collection apertures. They are especially applicable in the case that autocorrelation is unknown and only 1-D or 2-D finite data samples are available. However, LS-based minimum variance (MV) spectral estimators are not widely used due to intensive computational burden. This thesis proposes 1-D and 2-D fast computation solutions. The "basis" for the fast solutions is the exploitation of the structures of the various inverse relationships, which express the inverse of covariance matrices (or covariance-like quadratic-data-matrix product matrices in the case of the least-squares algorithms) in terms of the parametric autoregressive (AR) or linear prediction (LP) terms. Meanwhile, all lower-order solutions are obtained by the fast computation solutions without additional computations, unlike direct solution approaches. This is useful when one does not know the correct order, so several orders are evaluated for the best result using one algorithmic running of the fast algorithm(s).

Deep Ultraviolet Solid-State Laser Development
There is a new possibility of generating a deep ultraviolet laser. With a recent advancement in material development, a new nonlinear optical crystal has provided a greater damage threshold than current materials. This thesis examines the possibility of using this crystal at deep ultraviolet wavelengths. The current model illustrates the inadequacy of the crystal performing a direct doubling conversion using a 404 nm source. Observation of a 202 nm signal when the crystal is placed in front of a 404 nm source verifies the inaccuracy of current Sellmeier equations. Additional verification is also illustrated when generation of 235 nm is found at an angle of 11 degrees less than the model prediction. Possible electro-optic Q-switching is examined. Electro-optic modulation measurements show a very small refractive index change. When angle tuning, a greater depth of modulation is noted, however, full extinction of the beam could not be achieved. To improve efficiency, intra-cavity resonant doubling is investigated. Several cavity stabilization schemes are implemented successfully. The cavity remains locked while being perturbed by outside forces and has less than 1% modulation on the signal under normal operating conditions. Continued improvement in crystal quality promotes the clarity and longevity in UV production. This new material provides a solution for industrial solid-state deep ultraviolet laser sources.

An Enhanced Dual-Path Delta-Sigma Analog-To-Digital Converter
The increasing demand for higher performance communication devices has fueled the research and development of wideband delta-sigma modulators in the last decade. Enhanced-split architecture has been proposed recently and this architecture features several advantages over the conventional ones; it provides enhanced noise shaping without any stability issues. Unlike multi-stage noise shaping (MASH) architecture, this does not suffer from quantization noise leakage and shows equivalent analog complexity. This research proposal focuses on the implementation of an analog-to-digital converter (ADC) employing the novel architecture in order to attain a high dynamic range for a relatively wide-band signal bandwidth (80-dB of signal-to-noise ratio for the 2-MHz of signal bandwidth.)

OSU Fee Tracking
Internet applications have been playing a very important role in most people's life. This project has been widely used by staff and students in OSU. With this system’s support, it is much easier for staff to manage the complicated fees such as I/E fee, course fee, resource fee, and etc. It also simplifies and standardizes the workflow of management to prevent the happening of errors. For students, it is more convenient to view the latest fees and download the Fee BOOK.

Latest technologies including N-tier architecture, design pattern and .Net framework have been integrated. Milestone and project management methodologies have been adopted to control the risk of software development.

Reinforcement Learning for Network Routing
Efficient routing of information packets in dynamically changing communication networks requires routing policies that adapt to changes in load levels, traffic patterns and network topologies. Reinforcement Learning (RL) is an area of artificial intelligence that studies algorithms that dynamically optimize their performance based on experience in an environment. RL, thus, is a promising framework for developing adaptive network routing algorithms and there have been a number of proposed RL-based routing algorithms. In this project, we developed an infrastructure for evaluating RL-based routing mechanisms and use it to evaluate and compare a number of existing algorithms under various network conditions.

A Wideband Low-Power Continuous-Time Delta-Sigma Modulator for Next Generation Wireless Applications
Delta-Sigma (ΔΣ) analog-to-digital converters (ADCs) are widely used in the wireless transceivers. Recently, the continuous-time (CT) ΔΣ ADCs gain growing interesting in the wireless applications for their lower power consumption and wider input bandwidth compared with the discrete-time (DT) counterparts.

In this thesis, the design of a wideband low-power CT ΔΣ modulator for next generation wireless applications is proposed to achieve 10-bit dynamic range within 25 MHz signal bandwidth. In the system level, a low-power, mainly feed-forward architecture is used to realize the loop filter. Feed-in branches are added and optimized to eliminate the out-of-band peaking in the signal transfer function. In the circuit level, two-stage operational amplifiers with class-AB output stages are used to implement low-power active RC integrators. Capacitor tuning is used to compensate the variation of RC time constant. In addition, a fast current adder, an 11-level internal flash ADC and three current feedback DACs are also integrated on the chip which was manufactured with TSMC 0.18 μm CMOS technology. The test results show that the modulator draws less than 10 mA from the 1.8 V supply voltage.

Intelligent Assistants -- A Decision -- Theoretic Model
Building intelligent assistants has been a long-cherished goal of AI and many were built and fine-tuned to specific application domains. Previously, we proposed a domain-independent decision-theoretic model of assistance, where the task is to infer the user's goal and take actions that minimize the expected cost of the user's policy. Recently, we extended this work to domains where the user's policies have rich relational and hierarchical structure. Our results indicate that relational hierarchies allow succinct encoding of prior knowledge for the assistant, which in turn enables the assistant to start helping the user after relatively small amount experience. The use of relational hierarchies enables us to leverage the advantages of both relational and hierarchical models for reinforcement learning. We propose to use this relational hierarchies to handle several other extensions that include the possibilities of user and assistant acting in parallel, user forgetting goals or changing the subgoals.

Design Techniques for Delta-Sigma Data Converters
In the first part of this presentation, design techniques for a 0.8V, 88dB dual-channel audio delta-sigma DAC with headphone driver are described. Time-interleaved architectures for interpolation filter, delta-sigma modulator, and dynamic element matching (DEM) are proposed to minimize their hardware requirements.

In the second part, 3 new architectures for delta-sigma A/D conversion are proposed. First, a multi-cell delta-sigma ADC topology will be shown, which allows robust operation, programmability, and wide trade-off between resolution and power. Then, two types of quantization noise coupling in multi-cell delta-sigma ADC will be introduced to improve the noise shaping of modulator without degrading its stability conditions. Unlike conventional multistage noise shaping (MASH), its performance is insensitive to circuit errors. Generalizations to higher-order noise coupling will be provided. Next, the noise coupling will be extended to time-interleaved delta-sigma ADCs. These new architectures are suitable for wideband and low power application. Finally, prototype design based on proposed architectures will be shown to prove the effectiveness of the proposed concepts.

An Optimized SRAM Test Algorithm for Detecting Semiconductor Process Defects
A key feature of an SRAM-based monitoring technique involves a correlation between electrical test results and a visual inspection of defects on SRAM wafers. Due to the density of memory cells, an SRAM-based monitoring technique allows detection of various fabrication defects with higher efficiency. In order to detect electrical faults, various pattern testing algorithms are used to determine functionality of each memory cell within an SRAM memory array. The March pattern memory algorithm consists of a series of operations on each cell within an entire memory array. These operations include reading and writing of a logical 0 or 1 into each cell within the memory array. This project describes an implementation of a new SRAM pattern algorithm which improves the ability to detect fabrication faults and more efficiently monitor yield. A new algorithm is implemented with built-in memory testing methods from Teradyne FLEX tester, involving micro-codes and Visual Basic programming language.

Performance-Improving Techniques for Wireless Systems
In this thesis, maximum likelihood Doppler frequency estimation and phase noise suppression algorithms for Orthogonal Frequency Division Multiplexing (OFDM) systems are presented. A novel handover decision algorithm for wireless systems, called predictive base station switching (PBSS), is also introduced.

The maximum Doppler Frequency is the ratio of the speed of the mobile user and the carrier frequency. The Doppler frequency information of each mobile can be exploited to minimize the number of handover scenarios and to improve channel estimation. The estimation of this quantity in time-varying multipath channels is performed in this thesis by a frequency-domain approach that utilizes pilot subcarriers, which are commonly implemented in most practical OFDM systems. In the proposed estimator, the effect of the intercarrier interference (ICI) caused by the time-varying fading is taken into consideration with a proper model for accurate results. The Cramer-Rao bounds are also driven and simulation results are provided to quantify the performance of the algorithm.

This thesis also presents a maximum likelihood approach exploiting the OFDM pilot subcarriers to suppress phase noise due to imperfect local oscillators. This algorithm does not require perfect channel equalization and is applicable for the two common types of oscillators: phase-locked and free-running oscillators. Furthermore, doubly-selective fading is considered rather than assuming time-invariant and/or flat fading channels.

Finally, a new handover decision algorithm, PBSS, is presented. PBSS is designed for broadband wireless access (BWA) systems (where users can travel at vehicular speeds) that typically have small cell sizes due to high-data-rate transmission. High-mobility users of BWA systems usually need to perform frequent handovers, which degrades the overall network performance. PBSS uses mobile speed and direction information to reduce the number of handovers without degrading the received signal level. Simulation results show that PBSS performs better than algorithms only based on information of signal strength and distance, even when the users move randomly or accurate direction and speed information is unavailable.

Volume Analysis and Visualization
3D datasets acquire great importance in the context of Medical Imaging. In this thesis we survey and enhance solutions to problems inherently associated with 3D datasets - processing time, noise and visualization. Efforts include development of a toolkit to provide a multi-threaded processing platform to cut processing time, real time visualization and the use of the Graphics Processing Unit as a general purpose computing device.

Low Voltage Techniques for Pipelined Analog-to-Digital Converters
To realize pipelined ADCs in deep-submicron processes, low voltage techniques must be developed to work around problems created by limited supply voltages such as the floating switch dead zone, reduced SNR, and reduced OpAmp performance.

This thesis analyzes standard and low voltage design issues for pipelined ADCs and proposes a fully-differential implementation of the OpAmp Reset Switching Technique (ORST) as a suitable low voltage design solution. The technique uses a true fully differential MDAC structure with a switching common-mode feedback to achieve increased linearity and noise performance over the previously published ORST.

A pipelined ADC test chip is designed to implement the fully differential ORST technique as a proof of concept. The design also includes a simple, low power input sampling network that also allows an increased input signal range and saves power by removing the dedicated, front-end S/H.

Prototype performance demonstrates the fully differential ORST and shows sampling speeds of up to 60 MS/s, 51.4 dB SNR, 58.8 dB SFDR, and 49.7 dB SNDR for an 8-bit ENOB in a 0.18um CMOS process with a 1V supply. The 200 MHz input bandwidth also shows little change in the total distortion, demonstrating operation without a S/H.

Hybrid Electric Vehicle Active Rectifier Performance Analysis
In advanced hybrid electric vehicle development, performance and dependability are essential considerations in the design process. High efficiency is crucial in a successful design and fault tolerance is necessary to provide limp-home capability under faulted operating conditions. The reduction of electromagnetic interference is mandatory to reduce interference in communications and control systems, especially in military applications. This thesis is a performance analysis of several generator and active rectifier configurations for use in military hybrid electric vehicle applications. Simulation results are obtained using Matlab Simulink with experimental hardware testing for verification.

Fault tolerance is explored in generator design through the use of multi-phase generator configurations in both wye-connected and independent phase configurations. Passive rectifier investigations are included as a baseline for active rectifier performance comparison. Simple voltage-controlled active rectifier results are obtained with initial three- and six-phase generator configurations. Current-controlled rectifier models are then simulated with more advanced generator designs. In all simulations, performance is evaluated through harmonic analysis of rectifier input currents and output dc bus voltage, as well as input power factor measurements.

Scaled hardware testing is performed for verification of simulation results. Multiple generator configurations are represented through utilization of a three-phase, fully programmable source with various transformer configurations at the output to achieve six-phase capability. Several active rectifier configurations are obtained through the use of configurable Powerex H-Bridge IGBT assemblies with control provided using an Opal-RT hardware-in-loop rapid prototyping system.

Link to dissertation

Simulation and Analysis of Noise in CMOS Imagers
Noise is becoming an increasingly important factor in designing CMOS imagers at low light levels. Both thermal noise and 1/f noise of the transistor are contributing factors. While correlated double sampling reduces some noise effects, better techniques are needed to simulate and analyze noise characteristics in imagers. Such a technique is employed to simulate both noise components and compare the results to an older technique developed by Robert J. Kansy.

Low-voltage Data Converters
With the growing demand for portable/consumer electronics, such as digital audio/video (AV), the downscaling of device dimensions, which enables the integration of an increasing number of transistors in a single chip, is mandatory. This trend also continuously pushes the power supply voltage down to reduce the power consumption and improve the reliability of gate dielectrics. While the reduction of power supply voltage is of great benefit to the essential digital blocks in the system like data storage and digital signal processing, it makes it hard to operate the important and indispensable analog building blocks such as data converters and drivers.

In this thesis, the novel structures for the low-voltage digital-to-analog converter (DAC) and analog-to-digital converter (ADC) are presented. The research contributions of this work include (1) a sub-1V audio ?S DAC with one opamp used per channel to implement D/A conversion, 1st-order FIR and 2nd-order IIR filtering, as well as power amplification for the headphone, (2) a sub-1V pipelined ADC with the novel MDAC based on a low-voltage track-and-hold amplifier. Two prototypes, one is a 0.8V, 88dB dual-channel audio ?S DAC with headphone driver, the other one is a 0.8V, 10-bit, 10MS/s pipelined ADC were fabricated to verify the functionality of the proposed structures in standard CMOS processes.

Design Techniques for PVT Tolerant Phase-Locked Loops
The continued scaling of deep-submicron CMOS technology enables low-voltage high-frequency phase-locked loops (PLLs) to be fully integrated in complex mixed-signal systems. However, the fluctuations due to the manufacturing process and variations in the environmental conditions, such as supply voltage and temperature, are also significantly increased. As a result, the performance of PLLs that are susceptible to process, voltage, and temperature (PVT) variations are dramatically affected. Hence, to truly benefit from process scaling, PVT tolerant designs are imperative for the design of high-performance PLLs.

In this dissertation, circuit techniques that can mitigate the impacts of PVT variations on PLL performance are presented. In the context of ring voltage-controlled oscillator (VCO) based PLLs, an on-chip calibration technique for reducing supply voltage sensitivity is described. This method rejects supply noise while avoiding the use of supply regulation, which makes it more desirable in the design of low-voltage high-performance ring VCOs. In a wide-tuning range LC-VCO based PLL frequency synthesizer, design techniques for maintaining a constant loop bandwidth are presented. The proposed circuit techniques are validated by measurement results obtained from the prototype chips. The concepts presented in the context of the analog PLL implementations can be easily migrated to digital PLLs.

Link to dissertation

Design and Analysis of a 5GHz 0.18um CMOS LC-VCO and Frequency synthesizer For IEEE 802.11a WLANs
Voltage Controlled Oscillator (VCO) and Frequency synthesizers are critical components for frequency translation and channel selection in wireless transceivers. The purpose of this project is to design a 5GHz 0.18um CMOS LC-VCO and Frequency Synthesizer for IEEE 802.11a WLANs. This design is based on charge pump PLL technology, and use Dual-Modulus Prescaler (DMP). Design specifications include: Phase noise: less than -110dBc/Hz @ 1MHz offset, Turning range: 4.9-5.85GHz, and quadrature output.

Comparison and Impact of Substrate Noise Generated by Clocked and Clockless Digital Circuitry
Delay insensitive asynchronous circuitry provides significant advantages with respect to substrate noise due to localized switching. The differences between the substrate noise from NULL Convention Logic (NCL) and traditional Clocked Boolean Logic (CBL) are described and analyzed based on measured results. A test chip fabricated in the TSMC 0.25um process shows that a pseudo-random number generator implemented with NCL generates 23dB less substrate noise compared to the equivalent synchronous design. In a larger scale digital circuit, the substrate noise improvement offered by an asynchronous 8051 processor over its synchronous counterpart was still nearly 10 dB. The effect of this substrate noise on an analog circuit was explored with a delta sigma modulator (DSM) example. The SNR performance of a second order DSM was not affected by the substrate noise from the NCL 8051 processor while it experiences up to 15dB degradation when the CBL 8051 processor is clocked near integer multiples of the DSM sampling frequency.

Digital PLLs for Multi-GHz Clock Generation
A digital implementation of PLLs has several advantages in comparison to their analog counterparts: easy scalability with process shrink, eliminating the noise susceptible analog control for a voltage controlled oscillator (VCO) and the inherent noise immunity of digital circuits. Recently, several digital PLLs (DPLLs) have been reported, which demonstrate the ability of a digital implementation to achieve the performance of analog PLLs. The drawback of most of the reported DPLLs is the bang-bang behavior of the phase detector when the DPLL is in a lock condition. This poses an upper bound on the bandwidth of a DPLL and thus limits its capability to track an input signal. Research described in this thesis is focused on developing new digital PLL architectures, that overcome this bandwidth limitation in linear as well as in bang-bang digital PLLs.

A systematic design procedure for a second-order digital phase-locked loop is proposed. The design procedure is based on the analogy between a type-II second-order analog PLL and a digital PLL. A new linear digital PLL architecture which brakes noise-bandwidth tradeoff is presented. It employs a stochastic time-to-digital converter (STDC) and a high frequency delta-sigma dithering to achieve a wide PLL bandwidth and low jitter at the same time. The measured results obtained from the prototype chip demonstrate a significant jitter improvement with the STDC. A bang-bang digital PLL employing an adaptive tracking technique and a novel frequency acquisition scheme achieves a wide tracking range and fast frequency acquisition. The experimental results illustrate a tracking bandwidth improvement of 100%. As result, the proposed DPLL is suitable for applications employing spread-spectrum clocking.

Advances in Side-Channel Cryptanalysis: MicroArchitectural Attacks
Cryptographic devices leak timing and power consumption information that is easily measurable, radiation of various levels, and more. Such devices also have additional inputs, other than plaintext and keys, like voltage, which can be modified to force the device to produce certain faulty outputs that can be used to reveal the secret key. Side-channel cryptanalysis uses the information that leaks through one or more side channels of a cryptographic system to obtain secret information.

The initial focus of side-channel research was on smart card security. There are two main reasons why smart cards were the first type of devices that was analyzed extensively from the side-channel point of view. Smart cards store secret values inside the card and they are especially designed to protect and process these secret values. Therefore, there is a serious financial gain involved in cracking smart cards, as well as, analyzing them and developing more secure smart card technologies. The recent promises from Trusted Computing community indicate the security assurance of storing such secret values in PC platforms, c.f. [99]. These promises have made the side-channel analysis of PC platforms as desirable as that of smart cards.

The second reason of the high attention to side-channel analysis of smart cards is due to the ease of applying such attacks to them. The measurements of side-channel information on smart cards are almost "noiseless", which makes such attacks very practical. On the other hand, there are many factors that affect such measurements on real commodity computer systems. These factors create noise, and therefore it is much more difficult to develop and perform successful attacks on such "real" computers within our daily life. Thus, until very recently the vulnerability of systems even running on servers was not "really" considered to be harmful by such side-channel attacks. This was changed with the work of Brumley and Boneh, c.f. [21], who demonstrated a remote timing attack over a local network.

Because of the above reasons, we have seen an increased research effort on the security analysis of the daily life PC platforms from the side-channel point of view. Here, it has been especially shown that the functionality of the common components of processor architectures creates an indisputable security risk, c.f. [1, 2, 5, 14, 73, 80], which comes in different forms.

In this thesis, we focus on side-channel cryptanalysis of cryptosystems on commodity computer platforms. Especially, we analyze two main CPU components, cache and branch prediction unit, from side-channel point of view. We show that the functionalities of these two components create very serious security risks in software systems, especially in software based cryptosystems.

Simulation-Based Optimization of Football Defenses
We develop a system for simulation-based optimization of defensive formations for American football. The first component of the system is an environment for simulating football plays with real physical interactions between players and their surroundings. The simulator is built on the AGEIA PhysX engine, which incorporates rigid body dynamics and collision detection. The simulator allows a user to design, visualize, and execute distinct plays for each offensive player. In addition, the camera angle and zoom can be adjusted to suit the user's needs. The second component of the system is a genetic algorithm that uses the simulator to optimize the defensive formation based on the offense's playbook and its likelihood of running each play. We show that this technique effectively tunes defenses to a variety of game situations.

Improved Fabrication Process Monitoring with New March SRAM Algorithm
New technology introductions occur frequently and require advanced fabrication monitoring techniques. SRAM-based monitoring has been widely used to identify critical elements of design and manufacturing. Key feature of SRAM-based monitoring involves development and implementation of March algorithms which help determine circuit performance and detect faults caused by various fabrication steps. This project covers a research and implementation of new SRAM March algorithm for detection of fabrication faults. New implemented March algorithm improves coupling faults coverage for idempotent and state coupling cases.

GPU Programming for Image Compression and Interaction
This paper will provide a survey of image compression techniques for fast interaction of large images. Then the implementation of a luminance-based color scheme combined with the encoding techniques pioneered by S3TC, FXT1, and DXTn will demonstrate a high yield compression that takes advantage of current graphics hardware. Results of 8.73:1 can be observed, allowing images over one gigabyte in size to fit on a 128mb video card and be viewed with a smooth pan and zoom experience.

Improving End-Users' Involvement in Privacy and Security Management
The proposed research is aimed at addressing the question of whether or not Internet users can be successfully involved in the privacy and security management. Prior research seems to be skeptical about that, since no good evidence of successful involvement has been obtained so far. Despite the fact that privacy has long been reported to be of utmost concern for the online users, they are rarely proactive when it comes to protecting it, which can result in a whole specter of privacy violations: from undesired tracking of users' online activity to numerous spam messages inundating mailboxes to identity theft and monetary losses. Our analysis indicates several underlying problems that prevent users from being proactive: little awareness of how the personal data is collected and used, improper assessment of risks and benefits associated with the exchange of personal information, and a lack of incentives to use privacy protection tools. In this research we are going to closely investigate these problems and suggest solutions to each of them.

Noise Coupling Techniques in Multi-Cell Delta-Sigma Modulators
High performance multi-cell delta-sigma modulators are a preferred choice in applications which require programmability. Multi-cell delta-sigma modulators with M unit cells provide 10log10(M) SQNR improvement for the same thermal noise and bias power due to the uncorrelated quantization noises of the M unit ADCs. This concept is used in this thesis to illustrate novel third-order and fourth-order noise shaping structures using split ADC of second order, and hence providing higher-order noise shaping with the same thermal noise and bias power as that of a conventional second-order structure. The additional SQNR improvement due to split ADC can be traded off with power. Switched capacitor implementations are also proposed to confirm that both third-order and fourth-order noise shaping structures require only two opamps by using self-enhancement technique in a second-order single stage. The novel third-order structure discussed in this thesis is compared to a conventional second-order, a single-stage third-order and a 2+1 MASH in terms of performance, stability and sensitivity to opamp non-idealities. Similar comparisons are done for the proposed fourth-order structure with a conventional second-order, a single-stage fourth-order and a 2+2 MASH ADC. Simulation results show that the novel noise shaping structures for third and fourth order are highly robust, and show performance similar to other existing structures for the same order of noise shaping.

Link to thesis

A Dual-Path 2-0 MASH ADC with Dual Digital Error Correction
This dissertation presents a dual-path 2-0 MASH (Multi-stAge noise -SHaping) ADC with digital corrections of DAC mismatch error and quantization noise leakage. By using these two techniques, the requirements for the analog circuits are greatly relaxed. The dual-path structure generates two outputs, one only composed of conversion errors, the other input signal plus conversion errors. For the above two correlation algorithm, the input signal is the largest interfere. Hence, the first output is suitable for a correlation operation, greatly speeding up the correlation based techniques, while the second serves as the final output after removal of the DAC error and noise leakage.

The dissertation also proposes a new Dynamic Element Matching (DEM) technique, named Segmented Data Weighted Averaging (SeDWA), for application in a multi-bit Delta-Sigma Modulator (DSM). In SeDWA, the DAC elements are divided into several subsets with Data Weighted Averaging (DWA) applied in each set. This allows a simpler and faster implementation, and the selecting sequences for the DAC elements are more randomized than in conventional DWA. It reduces pattern tones, but still provides mismatch error shaping. In the simulated Power Spectra Density (PSD), no in-band pattern tones were observed, and only a moderate rise of the noise floor. Therefore, higher Spurious-Free Dynamic Range (SFDR) was achieved. The implementation of SeDWA can be simpler and faster than that of conventional DWA, making it suitable for high-speed applications.

To verify the first technique, an experimental dual-path 2-0 MASH DSM was built. The split structure allows fast convergence and improved accuracy for the correction. Using a 20 MHz clock, the prototype chip achieved an 84 dB dynamic range in a 1.25 MHz signal band, when fabricated in CMOS 0.18um process.

Strained Silicon
Strained silicon is used to increase mobility in 90nm gate lengths and shorter MOSFETs. Strain alters the energy band diagram and material properties causing improvements in device performance independent of traditional geometrical scaling. Device design considerations are discussed for process integration reasons.

Gray Codes and Their Applications
An n-bit binary Gray code is an ordered set of all binary strings of length n. The special property of this listing is that Hamming distance (number of bits that are not equal) between consecutive vectors is exactly 1. If the last and first code words also have a Hamming distance 1 then the code is said to be cyclic. For higher radix () Gray codes, any two radix k strings differ in exactly one digit by.

Over the last 4-5 decades binary Gray codes have found applications in diverse areas: VLSI testing, signal encoding, ordering of documents on the shelves, data compression, statistics, graphics and image processing, processor allocation in the hypercube, hashing, computing the permanent, information retrieval, puzzles such as the Chinese rings and towers of Hanoi, designing efficient combinatorial algorithms, etc.

This research proposal addresses problems dealing with the design of new types of Gray codes for certain problems and new applications of existing types of both binary and non-binary Gray codes over various distance metrics. It is shown how properties of certain Gray codes can be used to solve problems arising in different domains. Design of new types of Gray codes to solve specific types of problems are also shown. Results already obtained in this direction are shown. Open problems which need further investigation are then shown.

Low Noise Clocking for High Speed Serial Links
As the functionality of digital chips continues to increase dramatically, chip-to-chip communication bandwidth must scale accordingly to avoid constraining the overall system performance. Therefore, high speed transceiver design has become an important research topic. In particular, the performance of the circuits that are responsible for timing accuracy are important as bit periods continue to shrink. Furthermore, in order for these circuits to have a true impact on the performance of the system, they must use unique architectures to achieve timing accuracy rather than simply trading power consumption for performance.

This talk discusses issues related to the timing circuits on both the transmit and receive side of the link. On the transmit side, a phase locked loop (PLL) is used to generate the clock that tells the driver when to start and stop driving the current bit onto the channel.

On the receive side, a clock and data recovery (CDR) circuit is responsible for properly centering the sampling clock in the middle of the bit period. Design techniques to achieve good timing performance in both the PLL and CDR are proposed. Specifically, the PLL incorporates a supply regulated tuning scheme to combat the high levels of supply noise present in large digital chips and a resistor-based charge pump to reduce the charge pump flicker noise contribution. The CDR uses oversampling to decouple the tradeoff between two important performance metrics: jitter generation and jitter tolerance.

To validate the proposed ideas, both a PLL test chip and a CDR test chip are presented. The PLL operates from 0.5GHz to 2.5GHz and achieves 2.36ps rms jitter using a ring voltage-controlled oscillator. The power consumption scales favorably with frequency, using much less power at lower frequencies where less power is needed. The CDR operates up to 3.6Gbps with a BER of less than 10-12. The measured jitter tolerance corner frequency was improved by 30x from 1MHz to 30MHz without increasing recovered clock jitter.

A Wideband Low-Power Continuous-Time Delta-Sigma Modulator for Next Generation Wireless Applications
While most of the delta-sigma ADCs for wireless application are implemented by using switch-capacitor techniques which are also referred as discrete-time (DT) delta-sigma modulators (DSMs) mainly due to mature design methodologies and robustness, more and more continuous-time (CT) delta-sigma ADCs are reported and show attractive performance.

In this thesis proposal, the design of a wideband low-power continuous-time (CT) DSM for next generation wireless applications is proposed to achieve 10-bit dynamic range within 25MHz signal bandwidth. In the system level, a low-power, mainly feed-forward architecture is used to realize the loop filter. Feed-in branches are added and optimized to eliminate the out-of-band peaking in the signal transfer function (STF). In the circuit level, two-stage operational amplifiers (OpAmps) with class-AB output stage are used to implement low-power active RC integrators. In addition, a fast current adder, 11-level internal flash ADC and three current feedback DACs are also integrated on the chip which is realized in 0.18μm CMOS technology. The simulation shows that the chip draws less than 10mA from the 1.8V supply voltage.

Instruction Fetching, Scheduling, and Forwarding in a Dynamic Multithreaded Processor
Dynamic multithreaded processors attempt to increase the performance of a single sequential program by dynamically extracting threads from sources such as loop iterations. The scheduling of instructions in such a processor plays a vital role in the amount of thread level parallelism that can be extracted and thus the overall system performance. Three new systems are presented in this thesis to increase the performance of instruction scheduling and value forwarding in a dynamic multithreaded processor.

Conflicts within the instruction cache from multiple threads requesting the same cache blocks reduced instruction fetch performance. A new instruction scheduling and fetching method is presented that uses the unique nature of the dynamically generated threads to increase fetch performance while keeping the complexity of the instruction cache low. Performance for this new fetching scheme is on par or better than the current instruction fetching method used by the simulated processor.

The overall performance of a dynamic multithreaded processor is limited by inter-thread dependencies that arise from generating threads that are not fully independent or parallel. A new inter-thread forwarding system is presented that speeds up the forwarding of values between threads, thus reducing the number of stalls from inter-thread dependencies. To further reduce the number of stalls, a critical path system is implemented that dynamically identifies and prioritizes instructions that produce inter-thread dependency values.

WebGen Version 2: Automatic Web-Script Generator for Web-Based GIS/Database Applications
WebGen 5 is a software tool for generating Web scripts automatically for Web-based GIS/database (WebGD) applications. WebGen 5 is implemented as a collection of templates. WebGen 5 Version 1 generates six types of Web scripts, i.e., search, select, edit, information, and action scripts for each table and a treeview script. It also generates from the database metadata the configuration file that provides the specifications for the first five types of Web scripts. With WebGen 5 Version 2, additional configuration files that allow user customization of Web scripts and linking of Web scripts can be used. The field layouts in the generated edit and information forms can be also specified. Templates and configuration files are written in PHP. The Web scripts generated by them are also in PHP. We are now using WebGen 5 Version 2 in real Web applications. The time required for creating Web scripts has been significantly reduced, and the configuration files are easy to produce. One of the applications contains more than 700 tables in the database, and hence more than 3500 scripts are generated.

Getting to Local Information: The Role of Different Costs
Finding information can cost a significant amount of time, even when the information is already stored on the user's local computer system. There is significant research aimed at reducing these time costs, but little research into exactly what these costs are or how they impact people's use of tools and technologies to access local information. This thesis presents a methodology for investigating such issues, and uses the methodology to report empirical results on ways people access local information and how these ways tie to different types of costs. Our results fill in gaps in what is known about the problem of accessing local information, thereby helping to inform technological solutions to the problem.

Computationally Efficient Substrate Noise Coupling Estimation in Lightly Doped Silicon Substrates
A Z-parameter based macromodel to characterize the substrate noise coupling for lightly doped substrates is developed in this thesis. The cross coupling impedance between two contacts is modeled using an improved geometric mean distance model and the self impedance is modeled using the contact geometry.

The proximity effects that influence the self impedance at close separations are accounted for, by adopting the conventional paneling approach. The model in conjunction with paneling developed for two contacts is extended to multiple contacts.

The relative errors due to the macromodel as compared to simulation and measurement results are within acceptable limits.

Link to thesis

Interactive 3D Line Integral Convolution on the GPU
The Line Integral Convolution (LIC) is a mainstay of flow visualization. It is, however, computationally intensive, which limits its interactivity. Also, when used to view 3D vector fields, the resulting images are dense and cluttered, making it difficult to perceive the flow on the interior parts of the field. This thesis describes research to make the 3D LIC more interactive by implementing it on the GPU. It also includes methods to improve the clarity of the 3D LIC images. The volume dataset and a 3D noise volume are placed in GPU memory as 3D textures. The GPU is then used to perform the LIC computations and display the resulting volume. This allows the user to dynamically adjust LIC parameters and derive more insight into the 3D flow field. Various techniques such as introduction of sparsity and the use of stereographics help to de-clutter the scene. Resulting images and timing benchmarks are included.

Link to thesis

Volume-Volume Matching
Oftentimes in visualization, the goal of using volume datasets is not just to visualize them but also to analyze and compare them. In order to compare the two volumes, we cannot take all the voxels into consideration. The size of a typical volume data set is quite large (maybe a billion or more voxels), thus it is not feasible to compare all these voxels to all in the other volume set. This project uses optimization methods to find the best orientation for aligning a second volume data set with a first. Using these methods, we will be able to determine how well one medical data volume matches against a "normally-developed" volume of the same type.

Contact resistance and stability assessment in oxide-based thin-film transistors
This thesis focuses on two aspects of oxide-based thin-film transistors (TFTs), contact resistance and instability assessment.

First, determination of the contact resistance of ITO (indium tin oxide) on two wide-band gap semiconductors, ZnO (zinc oxide) and IGO (indium gallium oxide) is attempted and the effects of contact resistance on device performance is investigated. Both transistor and TLM (transfer length method) structures are used in the study and three material systems are employed: ZnO on SiO2, ZnO on ATO (aluminum titanium oxide), and IGO on SiO2. It is found that devices fabricated on thermal silicon oxide as the gate insulator yield either an indeterminate or negligible contact resistance and a ΔL of either negative or positive sign. Exact values could not be extracted for contact resistance measurements as data variability induced inaccuracy. Devices fabricated using ATO as the gate dielectric result in either an indeterminate or non-negligible contact resistance and a positive ΔL. This suggests that the dielectric material plays a role in determining the contact resistance as reactions may be taking place at the channel/insulator interface. It is also noted that the surface roughness for thermal silicon oxide is ~ 0.28 nm, while ATO is ~ 5.5 nm. This difference in surface roughness may contribute to the difference in contact resistance. Moreover, it is concluded that the device dimensions used in this study are too large to yield an accurate estimate of the contract resistance; smaller channel lengths should reduce the amount data variability.

Second, a methodology for assessing the stability of oxide-based TFTs is developed and implemented. This methodology involves constant voltage stressing over a maximum duration of 105 s (i.e., ~ 28 hours) and periodic evaluation of drain current-drain voltage and drain current-gate voltage characteristics during the stability test. This stability assesment strategy is first applied to three semiconducting materials: ZnO, ZIO (zinc indium oxide), and IGO, using thermal silicon oxide as the gate dielectric and similar trends are observe. Relatively stable devices are obtained for post-deposition anneal temperatures of ~ 600 °C for ZnO and IGO TFTs, and ~ 400 °C for ZIO TFTs. The presence of instabilities result in a positive shift in the turn-on voltage and clockwise hysteresis in the drain current-gate voltage transfer curves. Such instabilities are attributed to electron trapping near the channel/insulator interface. The stability a ZnO TFT fabricated using a spin-coat synthesized AlPO (aluminum phosphate) as the gate dielectric is also investigated. The ZnO/AlPO TFT showed distinctively different stability trends. This device is observed to be very unstable with a negative shift in the turn-on voltage and the presence of counter-clockwise hysteresis. Mechanisms for these instabilities are ascribed to insulator ion drift. It is shown that stable TFTs can be fabricated with oxide-based channel layers if a high quality insulator is available and if a post-deposition anneal at elevated temperatures is employed.

Link to thesis

Multi-Antenna OFDM Systems in the Presence of Phase Noise and Doubly-Selective Fading
Orthogonal frequency division multiplexing (OFDM), which has been very attractive for future high rate wireless communications, is very robust to channel multipath fading effect while providing high transmission data rate with high spectral efficiency. Multiple antennas can be combined with OFDM to increase diversity gain and to improve spectral efficiency through spatial multiplexing and space-time coding (STC). This dissertation focuses on the performance analysis and detection schemes of multi-antenna OFDM systems in the presence of phase noise and doubly-selective fading (channel is both time-selective and frequency-selective).

In space-time coded OFDM (ST-OFDM), channel time variations cause not only intercarrier interference (ICI) among different subcarriers in one OFDM symbol, but also intertransmit-antenna interference (ITAI). We quantify the impact of time-selective fading on the performance of quasi-orthogonal ST-OFDM systems by deriving, via an analytical approach, the expressions of carrier-to-interference ratio (CIR) and signal-to-interference-plus-noise ratio (SINR). We also evaluate the performance of five different detection schemes and show all these schemes suffer from an irreducible error floor.

Multiple-input multiple-output (MIMO) antennas combined with OFDM are very attractive for high-data-rate communications. However, MIMO-OFDM systems are very vulnerable to time-selective fading. We apply frequency-domain correlative coding in MIMO-OFDM systems over doubly-selective fading channels and derive the analytical expression of CIR to demonstrate the effectiveness of correlative coding in mitigating ICI.

When applied in fast fading channels, common ST-OFDM receivers usually suffer from an irreducible error floor. We apply frequency-domain correlative coding combined with a modified decision-feedback (DF) detection scheme with low complexity to effectively suppress the error floor of quasi-orthogonal ST-OFDM over fast fading channels.

Similar to single-antenna OFDM, MIMO-OFDM suffers from significant performance degradation due to phase noise and time-selective fading. After characterizing the common phase error (CPE) caused by phase noise and ICI caused by phase noise as well as time-selective fading, we then derive a minimum mean-squared error (MMSE)-based scheme to mitigate the effect of both phase noise and Doppler frequency shift. We also evaluate and compare the performance of various detection schemes combined with the proposed CPE mitigation scheme.

Throughout the dissertation, theoretical performance analysis is always presented along with corroborating simulations.

Link to dissertation

Performance studies of interleaving schemes for MIMO-OFDM systems
This report investigates the BER performance of a novel joint space-frequency interleaving. The new interleaver scheme distributes the coded bits evenly in space and frequency. Hence it can better exploit the spatial and frequency diversities available in the channel. Numerical results show that the proposed joint space-frequency interleaving scheme outperforms other frequency or space-frequency interleaving schemes by as much as 0.3-2dB for some propagation scenarios.

Multimedia Streaming Using Multiple TCP Connections
Packet loss, delay, time-varying bandwidth are the three main problems facing multimedia streaming applications over the Internet. The existing techniques such as Media-aware network protocol, network adaptive source and channel coding, etc. have been proposed to either overcome or alleviate these drawbacks of the Internet. But these techniques either need specialized codecs or require significant changes in the network infrastructure. In this thesis, we propose the MultiTCP system, a receiver-driven, TCP-based application-layer transmission protocol for multimedia streaming over the Internet. The proposed algorithm aims at providing resilience against SHORT TERM insufficient bandwidth by using MULTIPLE TCP connections for the same application. Our proposed system enables the application to achieve and control the desired sending rate during congested periods, by using multiple TCP connections and dynamically changing the receiver's window size for each connection, which cannot be achieved using traditional TCP. Finally, the proposed system is implemented at the application layer, thus no kernel modification is necessary, leading to easy deployment. To demonstrate the performance of the proposed system, we present simulation and experimental results on the PlanetLab network to demonstrate its advantages over the traditional single TCP based approach.

Oregon Relational Spatial Topology (ORST) Representation
We designed a concise way to store and manipulate GIS coverage data in a geospatial database. Our geospatial database is implemented with PostgreSQL and PostGIS. PostgreSQL is an object-relational database, and PostGIS supports various geospatial operations as an SQL extension. In our Oregon Relational Spatial Topology (ORST) approach, topological relationships among polygons, arcs, and points are represented explicitly. With this explicit representation of polygon data, such spatial operations as moving a point, merging a polygon, and splitting a polygon can be supported with relative ease. In order to populate this database, we developed a process for converting polygon data stored as an ESRI shapefile first to the ESRI E00 coverage format and then to the ORST representation. We also implemented the spatial operations discussed above.

Link to thesis

Load Testing of a J2EE Web Application
Load testing of any e-commerce application is crucial to ensure the availability of the application at peak load times.

This project performs load testing of the 'Loan Search' functionality of BrokerBlueprint.com which is an online subscription-based portal for mortgage brokers. The Loan Search functionality is used by mortgage brokers to find lenders for a customer's loan criteria.

OpenSTA was used to establish a performance baseline for 100 concurrent users using Loan Search. After the system's software and hardware parameters were tweaked, the Open suite was run again to ensure that the desired service level was met for the concurrent users.

Link to thesis

Update Programming – A Safe Approach to Software Maintenance
Software maintenance accounts for a large portion of the software development cost, particularly the process of updating programs either to adapt for requirement change or to enhance design or efficiency. Currently, program updates are generally performed manually by programmers using text editors. This is an unreliable method because syntax and type errors are easily introduced, not to mention logic and semantic errors. The problem with this method is viewing programs on a low level, namely, as streams of characters. Rather than the textual representation, we propose to view the programs as abstract data types and to update programs through programming updates in update languages. In this dissertation, we first study a specific program update problem, monadification, which is the process of automatic introduction of monads into functional programs. Later we investigate a more general problem of program updates and present an update language. We design a core calculus for the update language as well as its semantics and type system. Moreover, we study the problem of generic traversals, which itself is a means of reducing the effort for software maintenance, but also serves as a basis for implementing program updates and other metaprogramming tasks.

Link to dissertation

Database Design and Persistence using NHibernate
The number of enterprise applications being developed in the computer industry is fast increasing. In any kind of application software engineering plays an important role making the software more productive and maintainable and Databases form an important part of the enterprise systems to support the enterprise data.

The starting point in any project will be to analyze the requirements in which the customer feedback is to be greatly involved. An effort has been made to analyze the requirements and slowly evolve this analysis into a database applying known and proven software engineering methods.

Databases and Persistence Layers always go together. A new emerging technology NHibernate, a persistence framework, was adopted. An attempt was made to see the feasibility of this new technology to the existing domain problem, how well it fits in and its pros and cons.

Development Test Suite for FPGA TekBot Learning Platform
As the TekBots program expands into senior and graduate level classes at Oregon State University, so does the need arise for more complex learning platforms. These complex hardware platforms cannot be adequately tested in a manufacturing environment as we have done previously. Also, due to their complexity, these platforms require substantial collateral documentation to allow first-time users to quickly become productive learners.

This thesis details the development of a post-manufacturing test suite, known as OMICRON, to comprehensively test an FPGA learning platform. It also documents the development of a user guide for the board that explains user accessible features as well as providing the necessary startup information so students can quickly become acquainted with the new learning platform.

While developing OMICRON, a new feature surfaced that provides a cycle-accurate hardware testbench debugger for testing student component modules that are implemented within the FPGA. This functionality serves a practical as well as an educational use by enabling test generation for detecting logic errors at a hardware level.

Students can probe their own designs from an intuitive low-level command line interface once the designs have been loaded into the FPGA. The debugger can also be used to probe external circuits connected to the FPGA.

In addition to simple probes, the hardware debugger is able to output testbench bit vectors in a continuous flow, and simultaneously receive cycle-accurate vector results. These test vectors can either be manually constructed, or extracted from simulation software. This thesis shall also demonstrate this unique test flow. The use of the debugger will be included as part of the user guide.

Link to thesis

Design Techniques for Clocking High Performance Signaling Systems
In order for the aggressive scaling of transistors to truly benefit the performance of large and complex digital systems, the communication bandwidth between ICs must scale accordingly. However, interconnect technology does not scale as aggressively, making communication between chips the major bottleneck in overall system performance. In addition, supply voltage scaling, increasing device leakage, and increased noise make existing signaling circuits inefficient and difficult to scale.

This talk will present both analog and digital enhancement techniques to mitigate scaling related issues and improve the performance of building blocks used in high-speed signaling systems. A hybrid analog/digital clock and data recovery (CDR) architecture that improves the tracking range of traditional CDRs by an order of magnitude will be presented. This CDR also employs improved analog phase-locked loop architecture to circumvent fundamental scaling problems such as low voltages and reduced outputimpedances.

An all-digital CDR architecture that obviates the need for any analog components while achieving error-free operation will be discussed. Several digital signal processing techniques used to achieve this performance will be presented. Finally, a digital-to-phase converter (DPC) with a resolution that exceeds the state-of-the-art DPC resolution by an order of magnitude will be reported. The proposed DPC achieves better than 100 femto-second resolution. Measurement results obtained from prototype chips that validate the proposed design techniques will be summarized.

On-Chip Crosstalk Suppression Schemes using Magnetic Films for RF/Microwave Applications
The primary objective of the thesis research is to study novel schemes of on-chip crosstalk suppression employing magnetic films at microwave frequencies. Since extraction of various material properties of the magnetic films is essential for successful application of the proposed method, the research also involves development of a new material characterization technique using a grounded coplanar waveguide configuration.

The novel material characterization method allows for simultaneous extraction of complex permeability, permittivity, saturation magnetization and resonance line-width of magnetic films for microwave applications. Material characteristics have been extracted from the full-wave EM simulations using only S-parameters for three different ferrite samples over the frequency range of 1 to 10 GHz for different applied external DC magnetic fields. The extracted parameters have been compared with the input parameters as well as with the theoretical calculations based on previously reported research and were found to be in excellent agreement.

Crosstalk suppression is achieved by placing a magnetic film between circuit elements. A systematic study is carried out to determine the extent of crosstalk suppression for a variation in the magnetic films material and physical characteristics using a pair of coupled microstrips. The results are validated by full-wave EM simulations and fabricated on an RT/Duriod substrate. Effectiveness of crosstalk suppression is presented in terms of S-parameters and fractional power coupled between the microstrips. The results indicate that an improvement of over 90% crosstalk reduction can be achieved with optimum material and physical properties.

Cryptanalysis and Enhancement of Authentication Protocols
Authentication protocols play important roles in network security. A variety of authentication protocols ranging from complex public-key cryptosystems to simple password-based authentication schemes have been proposed. However, currently there is no fully secure authentication scheme that can resist all known attacks. When a user authentication is performed over an insecure network, additional problems arise due to the fact that the communication may be intercepted, or even altered, by an attacker. In general, one cannot assume that there is a secure channel between the client and the server.

We present specific cryptanalytic attacks on existing protocols and show their vulnerabilities in order to design more secure protocols. Particularly, we propose improved security schemes to overcome certain security defects with registration, login, and password/identifier-change schemes. We then propose new authentications schemes which are more secure against guessing, stolen-verifier, replay, denial-of-service, and impersonation attacks than the existing protocols.

Space time coding in MIMO system
Multiple input Multiple output (MIMO) technology is attractive to realize high speed wireless communications without increasing the transmission band-width as spectrum and bandwidth becomes more and more precious. Space time coding (STC) is a scheme employing multiple antennas to increase transmission rate or improve transmission quality. STC is being used widely in wireless local area network (WLAN) and wireless metropolitan area network (WMAN). However, there are still many unsolved or partially solved issues of STC. In this thesis, we propose a new STC design from cyclic design; Then a systematic method to design quasi-orthogonal space time block codes (QOSTBC) is proposed for an arbitrary number of transmit antennas, optimal rotation angles are also derived to achieve full diversity; We also propose an analytic method to derive the exact error probabilities of orthogonal space time block codes (OSTBC); An adaptive power allocation is introduced to improve the performance of OSTBC; Combining STC with continuous phase modulation (CPM) is a solution for mobile communications to use transmit diversity, in this thesis, we apply OSTBC to bineary CPM with modulation index h=0.5, then simplified receiver is developed; Finally, a decoding method is presented to reduce the complexity of QOSTBC without performance loss.

Link to dissertation

Characterization of a Digital Phase Locked Loop and a Stochastic Time to Digital Converter
A digital phase locked loop (DPLL) and a statistical time-to-digital converter (STDC) were previously fabricated in a 0.35µm, 3.3V SOI CMOS process. This work summarizes these designs and characterizes the measured performance. Simulations supplement the measurements where applicable.

The DPLL was found to reach a locked state under a limited range of input conditions. Evaluation of the DPLL's digitally controlled analog oscillator (DCAO) revealed that transistor mismatch resulted in a non-ideal tuning curve. Simulations and measurements of the DCAO phase noise showed good correlation.

The STDC circuit was characterized for several test chips. Measurement results show good matching between the chips for the same input conditions. The ability to achieve higher resolution than standard time-to-digital converters is demonstrated through simulations and measurements.

Link to thesis

SSD Online Services
The Services for Students with Disabilities (SSD) is the department responsible for providing reasonable accommodation to students with documented disabilities. Each term, SSD serves approximately 500 students and receives hundreds of requests for various services. These services range from alternative testing, alternative formats, notetaking, classroom relocation, and requests for tables and chairs to be placed in the classrooms. The number of requests has been growing steadily and in order to provide accommodations on a timely basis, SSD had to find an efficient way to handle student requests. In 2002 alone, the department handled requests for various accommodations in 300 classes. The process was very stressful and tedious.

This paper reports on a SSD’s effort to create a web application to reduce the numbers of hours required to manually process accommodation requests. This application focused on two areas where SSD believed it was possible to increase the productivity of the service coordinators and promoting SSD ease of requesting accommodation to students. The two areas are automation of various processes and web accessibility.

This program successfully reduced the amount of paper utilized and increased the efficiency of the program. Based on results of a significant reduction on time spent, SSD saw the opportunity to improve and change the way students requested all services. The new database permits students to monitor their own requests. Therefore, students would develop self-advocacy skills that will serve them well at the university and beyond. For these reasons, SSD proposed a new way to integrate all these services into one database.

Link to thesis

Automatic Program Generation for Scientific Computing
The code reuse problem is a common software engineering problem in scientific computing. As a prevailing programming language in many scientific fields, Fortran does not provide support to address this problem. One particular reason is that Fortran lacks the support for generic programming. By applying program-generation techniques, we developed two approaches to address the code reuse problem.

The first approach is to design a program generator for the equation-based specification of subroutines that can be generic in the dimensions of arrays, parameter lists, and called subroutines. We apply that approach to a real-world problem in scientific computing, which requires the generic description of inverse ocean modeling tools. In addition to a compiler that can transform generic specifications into efficient Fortran code for models, we have also developed a type system that can identify possible errors already in the specifications.

The second approach is to extend Fortran with the support for generic programming. The result is the language Parametric Fortran, which supports defining Fortran program templates by allowing the parameterization of arbitrary Fortran constructs. A Fortran program template can be translated into a regular Fortran program guided by values for the parameters. Parametric Fortran is particularly useful in scientific computing. The applications include defining generic functions, removing duplicated code, and automatic differentiation. The described Fortran extension has also been successfully employed implementing the generic inverse ocean modeling system.

Link to dissertation

Automation of Blanket Credit Registration
Almost every student in the School of EECS undergoes the process of Blanket Credit Registration wherein the student has to fill out the form for registration, meet the concerned professor and obtain his approval. The staff of the department has to maintain the details of the student and the Professor who has approved his/her registration and remind the faculty to grade the student at the end of every quarter. The goal of this project is to automate the currently manual registration process. In particular, our proposed system provides the students with the list of Courses that they could register and the list of Professors they could contact. Once the student makes the choice the system generates an email that is sent to the Professor. The email has a link that the Professor would use to approve/disapprove the request. If the Professor approves the request, an email is sent to the student informing him/her about the approval and the details of the Professor and the Student are stored in a database. The staff are also notified about the approval. If the Professor rejects the request, the student is notified about the decision. At the end of the quarter, the staff would login to the system and choose a Professor and the system would send a reminder email to the Professor with the list of students registered with him/her enabling the Professor to grade the students. This system was tested on a small sample of faculty, students and the staff in the school of EECS.

Link to thesis

Scaled Modeling and Simulation of Ocean Wave Linear Generator Buoy Systems
Accurate scaled modeling and simulation are critical to advancing ocean wave linear generator buoys. A 100th scaled model of ocean wave generator buoy systems is analyzed by solving the Navier-Stokes equations. These equations are numerically solved using CFD (Computational Fluid Dynamics) by implementing the front capturing method. In this thesis, winter and summer wave profiles are considered and the heave velocity of an oscillating buoy is studied in order to predict and to understand the power generated by the buoy. The results from the CFD simulations need to be compared with experimental data, thus a wave flume design from a dimensions perspective is presented, In addition, a 100th scaled permanent magnet linear generator design for high efficiency is presented.

The ocean buoy design is presented by drawing the transfer function in the heave motion. The frequency domain analysis is overlapped on the wave energy spectra for winter and summer conditions. MATLAB program scripts are listed for buoy dimensioning and linear generator design optimization. Also the linear generator design is verified using Maxwell-2D FEM code.

From simulations it was found that given the diameter of the ocean buoy of 4.5m, it can generate 70 kW rms power in winter, however the buoy can only generate 3.5 kW rms in summer with a damping factor of 0.25.

The optimized design of the PM linear generator designed using a 1mm air gap, with an efficiency of 96.5%, produces 2.2 W with a peak thrust of 30 N.

The damped frequency of heave motion is plotted and it is found that a 4.5m diameter buoy produces heave motion in the frequency range of the high energy spectrum.

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Efficient Far-Field Radio Frequency Energy Harvesting Passively Powered Sensor Networks
Passively powered devices are typically inductively coupled and harvest their power from the near field while operating within a few inches of the radiating source. Longer operating distance exceeding 10 meters is desired for applications in distributed sensor networks. An efficient method for far field power extraction from radio frequency (RF) energy is developed for long-distance passively powered sensor networks.

An RF-DC power conversion system is designed to efficiently convert far-field RF energy to DC voltages at very low received power. Two passive rectifier circuits are designed in a 0.25μm CMOS technology and the antenna for the system is printed on a 4-layer FR4 board with trace impedances carefully controlled. A high-Q resonator is used as matching network to passively amplify the input voltage to the rectifiers. At the circuit level, floating gate transistors are used as rectifying diodes to passively reduce the diode threshold loss in voltage rectification.

The 16-stage rectifier circuit can achieve 2 volt DC from input voltages as low as 80mV while achieving a passive voltage gain of 4.8. This system operates with received power as low as 14.8μW (-18.3dBm), corresponding to 27 meters operating distance from a 4W effective isotropically radiated power (EIRP) base station.

The 36-stage rectifier has maximum efficiency of 60% at 3 meters distance and can rectify input voltages as low as 50mV and has voltage gain of 6.4. This system operates with received power as low as 5.5μW (-22.6 dBm), corresponding to 42 meters operating distance from a 4W EIRP source. For distances of 15 meters, 1 volt DC is measured with 0.3μA load current at 906 MHz.

Anticipating Impacts
We present an approach for generating a character's response in anticipation of an impending impact. Protective anticipatory movement is built upon several simple actions that have been identified as response mechanisms in monkeys and in humans. These actions are parameterized by a model of the interaction based on the approaching object (the threat) and are defined in procedural rules according to heuristics. We guide the character to perform these actions while obeying physical limits for balance and maintaining characteristics taken from the behavior just prior to the interaction, in our case, a motion capture sequence. We combine our anticipation model with a physically-based dynamic response to produce animations where a character anticipates an impact before collision and reacts to the contact after the collision. We present a variety of examples including threats that vary in approach direction, size and speed.

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A Data-Driven Model of Pedestrian Movement
This thesis presents a model for simulating individual pedestrian motion based on empirical data. The model keeps track of a pedestrian's position, orientation, and body configuration and leverages motion capture data to generate plausible motion. Our model can automatically incorporate a pedestrian's physical limitations when making movement decisions, since it takes into account the current configuration of the character. Models can also be built for generating heterogeneous crowds by collecting motion capture data that includes children, the elderly, pedestrians in wheelchairs, and people on crutches. In this thesis, we present a 2D model for an able-bodied male and demonstrate the realism of our approach with a few small scale simulations and a larger crowd evacuation scenario. Furthermore, we compare the speed and density of pedestrians walking in single file to existing empirical results. The thesis concludes with a discussion of our model and offers suggestions for further research.

Information Space Mapping with Adaptive Multiplicatively Weighted Voronoi Diagrams
Traditional application of Voronoi diagrams for space partitioning creates Voronoi regions, with areas determined by the generators' relative locations and weights. Especially in the area of information space (re)construction, however, there is a need for inverse solutions; i.e., finding weights that result in regions with predefined areas. In this thesis, an Adaptive Multiplicatively Weighted Voronoi Diagram solution is formulated and a raster-based optimization method for finding the associated weight set is proposed. The basic algorithm is described, and several improvements are explored in detail, followed by algorithm's complexity analysis. The adaptive solution is successfully tested is successfully tested on a series of ideal/pathological cases, as well as using empirical data.

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Initial State Estimation for a Gun-Launched Projectile in a spatially Varying magnetic Field
Gun launched projectiles provide a significant challenge for the problem of navigation. Unlike aircrafts and missiles, whose initial conditions can be specified by the firing platform, the initial conditions for gun launched projectiles cannot be adequately specified, due to the inherent uncertainty in shot-to-shot launching conditions.

Smart weapons, or Precision Guided Munitions, promise to provide leap-ahead capability with regard to accuracy and engagement range for medium and large caliber projectiles. One of the most critical components of a smart weapon system is its sensor suite that provides position, orientation, and velocity information as the projectile flies down range so that effective control action can be taken in flight. Great strides have been made in creating very small and rugged Inertial Measurement Units (IMU) using MEMS accelerometers and vibrating gyroscopes. However, all IMU systems operate by integrating accelerometer and gyroscope measurements. Thus, they must be initialized at launch to produce sufficiently accurate position and orientation data. Currently, there is no adequate method to initialize IMU sensor suites on gun launched munitions.

This thesis investigates a novel concept for determining the full state of a projectile near the muzzle of the gun. The methodology relies on the gun system inducing a known spatially varying magnetic field in the vicinity of the muzzle of the gun. Using readings from a cluster of magnetometers embedded within the projectile, the full state of the projectile is determined by solving a nonlinear set of equations. Parametric trends of estimation accuracy versus magnetic field characteristics, number of projectile magnetometers, magnetic field errors, and magnetometer errors are reported.

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Low Power Scheduling Schemes that Consider Latency and Resource Constraints at Multiple Voltages
Power reduction can be achieved at many different levels, such as architecture, algorithm, logic, and transistor levels in circuit design. This thesis focuses on low power scheduling at the algorithm level. We present a latency-constrained scheduling and a latency and resource constrained scheduling, which minimize power consumption for the resources and registers operating at multiple cycles and voltages. The proposed schemes are based on the consideration of assigning most nodes to low voltage and reducing the number of registers simultaneously. We present a comprehensive scheduling methodology to decrease average power, peak power, and the number of registers during the scheduling stage. To target this goal, we propose the efficient algorithms to schedule DFG with the least power dissipation that satisfies the system constraints in timing and resources. Our benchmark shows that our approach has succeeded to reduce power in 12.99~41.97% in latency-constrained scheduling and 20.19~80.64% in latency and resource constrained scheduling for those multimedia kernels.

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Migrating ExcelForms to the .NET Framework
ExcelForms is a front end Excel-based application that supports Forms/3, a research language based on the spreadsheet paradigm, end-user software engineering features. The old implementation of ExcelForms performed poorly, and was considered unstable, not robust, and not scalable enough for our users’ needs. This project addresses these issues by implementing ExcelForms on the .NET framework.

Design of low-voltage high-performance PLL and frequency synthesizer
Phase-locked-loops (PLLs) are the key building blocks in mixed-signal integrated circuits, and are used in a wide variety of applications, such as clock generation, frequency synthesis, and clock recovery. Today’s rapid advancements in communication technology and the continued scaling of deep-submicron CMOS processes have made it more efficient and more necessary to increase operation frequencies of PLLs and frequency synthesizers at reduced supply voltages. The lowered voltage swings and increased process variations make high performance PLL design tolerant to noise and process variations extremely difficult. This is spurring a great demand for new circuit techniques in the design of low-voltage high-performance PLLs and frequency synthesizers.

Conventional methods employ voltage regulators to suppress supply voltage noise in ring oscillators at the cost of reduced voltage headroom. In the design of oscillators and PLLs at 1V supply, alternative techniques are preferred. We have proposed an on-chip calibration technique for reducing supply voltage sensitivity in ring oscillators. A 1V 0.13um CMOS prototype PLL demonstrates robust performance against VCO supply noise over operating frequencies of 0.5-2GHz. The measured rms jitter of the proposed PLL with on-chip calibration is 4.4ps for an operating frequency of 1.4GHz in the presence of 10mV 10MHz VCO supply noise, while a conventional design measures 31.3ps rms jitter.

In the second project, a 1.2V 0.13um CMOS fully integrated integer-N frequency synthesizer for 5GHz WLAN has been designed. To cover a wide tuning range and to maintain a low Kvco in the loop, traditional digital coarse tuning is used in LC-VCO based frequency synthesizers. However, in the presence of supply and temperature variations, a robust frequency calibration mechanism is needed. We have adopted an analog dual tuning technique. This proposed frequency synthesizer features: an adaptively tuned switched-capacitor coarse loop for fast locking, a constant loop bandwidth over all operating frequencies, and a linearized wide-tuning varactor.

Pulsed Ultra-Wideband: Transmission, Detection, and Performance
Ultra-wideband (UWB) communication has emerged as a very promising technology for short-range wireless applications, including high-speed multimedia transmissions and sensor networks. UWB system designs involve many different aspects covering analog and digital processing, channel estimation and modeling, and modulation and demodulation. Although UWB still faces many challenges, significant progress has been made to commercialize UWB systems. This thesis focuses on schemes to improve the performance and to lower the complexity of the UWB physical layer.

We first propose a frequency-hopped multi-band UWB system structure for higher throughput with better inter-symbol interference (ISI) immunity. This system is analyzed and compared to a single-band system. Pulse overlapping causes inter-pulse interference and may limit the system performance, especially in dense multipath environments. We then build a mathematical model with pulse overlapping considered and investigate the optimum linear RAKE receiver structure in such situation. The analysis is further is extended to systems that employ a prerake diversity combining scheme, in more realistic channel environments. The prerake scheme shifts RAKE receivers' related signal processing needs to the transmitter side and helps combat narrow-band interference.

To lower complexity, we develop a decision-directed autocorrelation (DDA) receiver, which offers more effective multipath energy capture at a lower complexity than the conventional RAKE receiver structures. Compared with transmit-reference receivers, the proposed DDA methods can considerably lower the noise level in the self-derived template waveform by operating in an adaptive decision-directed mode, thus improving the overall detection performance. There is little loss in energy efficiency since no reference pilots are required during adaptation.

Finally, we propose a hybrid modulation method that enables a heterogeneous network structure where users can flexibly choose a coherent RAKE receiver or a transmit-reference receiver structure. While neither type of receiver sacrifices performance loss by enabling the heterogeneous structure, the coherent RAKE receivers enjoy great performance advantages when further combined with forward error correction and iterative decoding methods.

Throughout the thesis, theoretical performance analysis is always presented along with corroborating simulations.

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Dual Path Delta-Sigma Modulator (DSM) with Digital Error Correction
Fast and highly accurate ADCs have been used in wide-band communication systems. Multibit delta-sigma modulators (DSMs) with low oversampling ratios (OSRs) offer a good option to implement these ADCs. Because of the low OSR, their performance is more vulnerable to the circuit nonidealities, such as DAC nonlinearity; also because of low OSR, there is less attenuation of in-band quantization noise.

Most of my research efforts are devoted to finding solutions to these challenges. Here, a dual-path DSM with digital correction of DAC errors and quantization noise leakage is proposed. A prototype DSM will be designed and fabricated to test the efficiency of the new structure. The targeted performance of the prototype DSM is as follows: 2MHz of signal bandwidth, 80dB SNDR, and OSR of 4.

Multi-Dimensional Sharpening Based on Predictive Bandwidth Extrapolation
Achieving the sharpened (enhanced detail) results of multi-dimensional data source using the LP Bandwidth Extrapolation (BWE) technique in spectral domain (or any transform domain) is the main purpose of this thesis. The evolution of sensor technology has provided acquisition scenarios in which the data format is inherently multi-dimensional, including hyper spectral imaging (HIS) sensors (s-spatial-dim by y-spatial dim by wavelength), interferometric synthetic aperture radar (ISAR) imaging (x-spatial-dam by y-spatial dim by elevation/height), and space-time adaptive processing (STAP) of radar (fast time [samples within a received pulse] by slow time (pulse-to-pulse sampling) by sensor array element number).

In all these applications, fully multi-dimensional signal processing that has the ability (1) to enhance the resolution of the final multi-dimensional analysis result, and (2) to provide reduced-dimension parametric features of the multi-dimensional data for purposes of data encoding/compression is highly desirable. This paper provides algorithmic techniques that for both capabilities.

This paper gives novel 2-D BWE approaches associated with fastcomputational algorithms, reported sharpening performances and other benefits of this technique. Furthermore, 3D linear prediction fast algorithms that have been developed by author estimate 3-D LP parameters in the original 3-D signal/space domain, in order to produce high-resolution results in the transform domain.

A Multi-bit Delta Sigma Audio Digital-to-Analog Converter
Digital-to-analog converters (DACs) with wide dynamic range and high linearity are required for high-end audio applications. A multi-bit delta sigma audio DAC, using a novel gain-correction technique, is described in this thesis. For widely varying on-chip RC time constant, the DAC gain can be accurately controlled by the correction circuitry. To overcome the nonlinearity caused by the mismatches of the internal unit-element DAC, a new dynamic element matching (DEM) algorithm, named split-set data-weighted averaging (SDWA), is proposed. In-band tones can be effectively removed by the proposed algorithm. Hardware implementation of SDWA is cost-effective and low-latency which makes it practical in high speed applications. A headphone driver integrated together with the analog reconstruction filter in the delta sigma audio DAC allows the designed DAC to driver the headphone directly.

An experimental headphone driver was designed and fabricated in a 0.35um CMOS technology. The prototype delta sigma audio DAC integrated with the headphone driver was built using the same technology. Simulation and measured results show that they both meet the requirements for a typical high-end audio system.

Link to disseration

Node and Topology Management for Content Distribution in Source Constraint Networks
As broadband Internet becomes widely available, Peer-to-Peer (P2P) applications over the Internet are becoming increasingly popular. Such an example is a video multicast application in which, one source streams a video to a large number of destination nodes through an overlay multicast tree consisting of peers. These overlay multicast-based applications, however, do not exploit the full bandwidth of every peer as the leaf nodes in the overlay multicast tree do not contribute their bandwidth to the system. On the other hand, all the peers in a properly constructed overlay mesh can contribute their bandwidth, resulting in high overall system throughput. This thesis provides details of an overlay topology that optimizes the bandwidth usage and also discusses design issues in node and topology management. The thesis also presents implementation details of the system. Finally the designed system is deployed on machines across PlanetLab and the results are presented. Large scale simulation results are also presented to verify robustness of the system.

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Interactive Football Playbook
This thesis presents a domain specific visual language designed to allow coaches to create content that exhibits the complex 2D interactions observed in the game of American football. Coaches can visually program the content by using symbols and drawing primitives similar to those that they currently use to design static playbooks. However, the result is not a static play, but animated primitives that move according to the programmed rules. The symbols and primitives represent rules that can be applied to the 2D synthetic players. The user can specify rules and run the simulation. At run-time, the rules are unified as a set of vector constraints. The resultant vector is used to animate the motion of the 2D player. The combination of football primitives and parameterization of those primitives allows the user