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A 79dB 80 MHz 8X-OSR hybrid delta-sigma/pipeline ADC

TitleA 79dB 80 MHz 8X-OSR hybrid delta-sigma/pipeline ADC
Publication TypeConference Paper
Year of Publication2009
AuthorsRajaee, O., T. Musah, S. Takeuchi, M. Aniya, K. Hamashita, P K. Hanumolu, and U. Moon
Conference NameIEEE Symp. VLSI Circuits
Pagination74 -75
Date Published06/2009
Conference LocationKyoto, Japan

A new delta-sigma modulator architecture is presented. The proposed implementation employs a pipeline ADC as the quantizer of a single-loop delta-sigma modulator and makes use of inherent delays of pipeline ADC stages to enhance overall noise shaping properties. With a 5MHz bandwidth and 80MHz clock, the measured dynamic range and SNDR of this prototype IC are 79dB and 75.4dB. The prototype chip is implemented in a 0.18 #x00B5;m CMOS process.