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A 1V downconversion filter using duty-cycle controlled bandwidth tuning

TitleA 1V downconversion filter using duty-cycle controlled bandwidth tuning
Publication TypeConference Paper
Year of Publication2008
AuthorsKurahashi, P., P K. Hanumolu, and U. Moon
Conference Name2008 IEEE Custom Integrated Circuits Conference - CICC 2008
Pagination707 - 710
Date Published09/2008
PublisherIEEE
Conference LocationSan Jose, CA
ISBN Number978-1-4244-2018-6
Abstract

This paper describes a downconversion filter which uses variable delay clocks to simultaneously perform downconversion mixing and filter bandwidth tuning. This method of bandwidth tuning is highly linear and applicable to low supply voltages. The test chip fabricated in a 0.18 mum CMOS process achieves 19.2 dBV IIP3 at 1 V and has a bandwidth that is tunable over a -50% range. The downconversion filter mixes and filters an 830 MHz input to a nominal 300 kHz bandwidth at DC.

DOI10.1109/CICC.2008.4672185