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Performance Evaluation of Dynamic Speculative Multithreading with the Cascadia Architecture

TitlePerformance Evaluation of Dynamic Speculative Multithreading with the Cascadia Architecture
Publication TypeJournal Article
Year of Publication2010
AuthorsZier, D. A., and B. Lee
JournalIEEE Transactions on Parallel and Distributed Systems
Pagination47 - 59
Date Published01/2010
Keywordsmulticore processors, multithreading processors, simulation, speculative multithreading

Thread-level parallelism (TLP) has been extensively studied in order to overcome the limitations of exploiting instruction-level parallelism (ILP) on high-performance superscalar processors. One promising method of exploiting TLP is dynamic speculative multithreading (D-SpMT), which extracts multiple threads from a sequential program without compiler support or instruction set extensions. This paper introduces Cascadia, a D-SpMT multicore architecture that provides multigrain thread-level support and is used to evaluate the performance of several benchmarks. Cascadia applies a unique sustainable IPC (sIPC) metric on a comprehensive loop tree to select the best performing nested loop level to multithread. This paper also discusses the relationships that loops have on one another, in particular, how loop nesting levels can be extended through procedures. In addition, a detailed study is provided on the effects that thread granularity and interthread dependencies have on the entire system.

Short TitleIEEE Trans. Parallel Distrib. Syst.