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A 250 mV, 352 µW low-IF quadrature GPS receiver in 130 nm CMOS

TitleA 250 mV, 352 µW low-IF quadrature GPS receiver in 130 nm CMOS
Publication TypeConference Paper
Year of Publication2010
AuthorsHeiberg, A. C., T. Brown, K. Mayaram, and T. S. Fiez
Conference Name2010 IEEE Symposium on VLSI Circuits
Pagination135 - 136
Date Published06/2010
PublisherIEEE
Conference LocationHonolulu, HI
ISBN Number978-1-4244-5454-9
Abstract

A low-IF quadrature GPS receiver consisting of a VCO, mixer and variable gain LNA is implemented in 130 nm CMOS. Consuming 352 μW from a 250 mV supply, it has the lowest supply voltage for an integrated receiver reported to date. The measured noise figure is 7.2 dB with a gain of 42 dB at a 10 MHz IF frequency. At a 1 MHz offset, the VCO phase noise is -112.4 dBc/Hz, resulting in an FoM of 187.4 dBc/Hz.

DOI10.1109/VLSIC.2010.5560322