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Digitally synthesized stochastic flash ADC using only standard digital cells

TitleDigitally synthesized stochastic flash ADC using only standard digital cells
Publication TypeConference Paper
Year of Publication2011
AuthorsWeaver, S. T., B. P. Hershberg, and U. Moon
Conference Name2011 Symposium on VLSI Circuits (VLSIC)
Pagination266 -267
Date Published06/2011
Keywords3-input NAND gates, analog comparator, analogue-digital conversion, CMOS digital integrated circuits, comparators (circuits), digital cell library, digital CMOS, digitally synthesized stochastic flash ADC, flash memories, Gaussian distribution, logic gates, size 90 nm, three-section piecewise-linear inverse Gaussian CDF function, Verilog code
Abstract

An ADC is synthesized entirely from Verilog code in 90nm digital CMOS using a standard digital cell library. An analog comparator is generated by cross-coupling two 3-input NAND gates. The random comparator offsets are used as the ADC references and are Gaussian. An implicitly aligned three-section piecewise-linear inverse Gaussian CDF function on chip linearizes the output. SNDR of 35.9dB is achieved at 210MSPS.