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Precise area-controlled return-to-zero current steering DAC with reduced sensitivity to clock jitter

TitlePrecise area-controlled return-to-zero current steering DAC with reduced sensitivity to clock jitter
Publication TypeConference Paper
Year of Publication2010
AuthorsMaghari, N., and U. Moon
Conference NameIEEE International Symposium on Circuits and Systems - ISCAS 2010
Pagination297 - 300
Date Published05/2010
PublisherIEEE
Conference LocationParis, France
ISBN Number978-1-4244-5308-5
Abstract

A precise return-to-zero current steering DAC is presented. This architecture uses a scaled switched-capacitor replica and a comparator to integrate the current over time, resulting in an accurate pulse. Without significant increase in the pulse height, the generated pulse can have its minimal value at the end of the DAC phase, hence minimizing the clock jitter effect. The proposed DAC can be used in continuous-time delta-sigma modulators to achieve high accuracy even in presence of the clock jitter. Simulation results are provided to prove the efficiency of this structure.

DOI10.1109/ISCAS.2010.5537858