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A 6b stochastic flash analog-to-digital converter without calibration or reference ladder

TitleA 6b stochastic flash analog-to-digital converter without calibration or reference ladder
Publication TypeConference Paper
Year of Publication2008
AuthorsWeaver, S. T., B. P. Hershberg, D. Knierim, and U. Moon
Conference Name2008 IEEE Asian Solid-State Circuits Conference (A-SSCC)
Pagination373 - 376
Date Published11/2008
PublisherIEEE
Conference LocationFukuoka, Japan
ISBN Number978-1-4244-2604-1
Abstract

A 6-bit stochastic flash ADC is presented. By connecting many comparators in parallel, a reference ladder is avoided by allowing random offset to set individual trip points. The ADC transfer function is the cumulative density function of comparator offset. A technique is proposed to improve transfer function linearity by 8.5 dB. A test chip, fabricated in 0.18 mum CMOS, achieves ENOB over 4.9 b up to 18 MS/s with 900 mV supply and comparator offset standard deviation of 140 mV Comparators are digital cells to allow automated synthesis. Total core power consumption when fs = 8 MHz is 631muW.

DOI10.1109/ASSCC.2008.4708805