A 6-bit stochastic flash ADC is presented. By connecting many comparators in parallel, a reference ladder is avoided by allowing random offset to set individual trip points. The ADC transfer function is the cumulative density function of comparator offset. A technique is proposed to improve transfer function linearity by 8.5 dB. A test chip, fabricated in 0.18 mum CMOS, achieves ENOB over 4.9 b up to 18 MS/s with 900 mV supply and comparator offset standard deviation of 140 mV Comparators are digital cells to allow automated synthesis. Total core power consumption when fs = 8 MHz is 631muW.