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Low-power and low-offset comparator using latch load

TitleLow-power and low-offset comparator using latch load
Publication TypeJournal Article
Year of Publication2011
AuthorsJung, Y., S. Lee, J. Chae, and G. C. Temes
JournalElectronics Letters
Volume47
Issue3
Pagination167 - 168
Date Published03/2011
ISSN00135194
Abstract

A low-power and low-offset latched comparator using dynamic offset cancellation and a latch load is proposed. A latch load at the first stage provides the second stage with a large conversion gain and large trigger voltage. It reduces the power consumption and offset voltage of the comparator. The effectiveness of the proposed structure was verified by SPECTRE simulations.

DOI10.1049/el.2010.3070
Short TitleElectron. Lett.