OREGON STATE UNIVERSITY

You are here

A 77dB SNDR, 4MHz MASH ΔΣ modulator with a second-stage multi-rate VCO-based quantizer

TitleA 77dB SNDR, 4MHz MASH ΔΣ modulator with a second-stage multi-rate VCO-based quantizer
Publication TypeConference Paper
Year of Publication2011
AuthorsAsl, S Z., S. Saxena, P K. Hanumolu, K. Mayaram, and T. S. Fiez
Conference Name2011 IEEE Custom Integrated Circuits Conference (CICC)
Pagination1 - 4
Date Published09/2011
PublisherIEEE
Conference LocationSan Jose, CA
ISBN Number978-1-4577-0222-8
Abstract

A VCO-based MASH delta-sigma ADC architecture is introduced that uses multi-rating of the two stages. The architecture allows for low power and high speed operation and is insensitive to the VCO linearity. To demonstrate this architecture, a prototype consisting of a first-order switched-capacitor (SC) integrator with a 4-bit quantizer operating at 100MHz is followed by a second-stage VCO-based ADC operating at 1.2GHz. The chip is implemented in a 130nm 1P8M CMOS process. The measured SNDR is 77dB for a 4MHz signal bandwidth with a power consumption of 13.8mW from a 1.3V supply. The resulting FoM is 298fJ per conversion.

DOI10.1109/CICC.2011.6055290