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A 31.3fJ/conversion-step 70.4dB SNDR 30MS/s 1.2V two-step pipelined ADC in 0.13μm CMOS

TitleA 31.3fJ/conversion-step 70.4dB SNDR 30MS/s 1.2V two-step pipelined ADC in 0.13μm CMOS
Publication TypeConference Paper
Year of Publication2012
AuthorsLee, H-Y., B. Lee, and U. Moon
Conference Name2012 IEEE International Solid- State Circuits Conference - (ISSCC)
Pagination474 - 476
Date Published02/2012
PublisherIEEE
Conference LocationSan Francisco, CA
ISBN Number978-1-4673-0375-0
Abstract

Analog-to-digital conversion with a signal bandwidth of 10 to 20MHz and ENOB of 11 to 12b has become a common requirement in many modern wireless communication systems where low power consumption is always a necessity. Typically, the traditional 2-step pipelined ADC is not considered a good candidate to meet these design specifications, since it is implemented with a power-hungry high-resolution flash sub-ADC and high-gain residue amplifier. Recently, however, low-power SAR architectures have been proposed as efficient replacements for flash-based sub-ADCs [1], especially since the conversion rate may be improved with the use of asynchronous clocking [2].

DOI10.1109/ISSCC.2012.6177097