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A 10b Ternary SAR ADC with decision time quantization based redundancy

TitleA 10b Ternary SAR ADC with decision time quantization based redundancy
Publication TypeConference Paper
Year of Publication2011
AuthorsGuerber, J., M. Gande, H. Venkatram, A. Waters, and U. Moon
Conference Name2011 IEEE Asian Solid-State Circuits Conference (A-SSCC)
Pagination65 - 68
Date Published11/2011
PublisherIEEE
Conference LocationJeju, South Korea
ISBN Number978-1-4577-1783-3
Abstract

The design of a Ternary Successive Approximation ADC (TSAR) with decision time quantization is proposed. The TSAR examines the transient information of the typical SAR comparator to provide full half-bit redundancy, an increased monotonicity switching algorithm, speed enhancements without inherent metastability, residue shaping effects, and stage skipping. A prototype is fabricated in 0.13μm CMOS employing on-chip statistical time reference calibration and supply variability from 0.8 to 1.2V. The chip consumes 84μW at 8 MHz for a FOM of 16fJ/C-S.

DOI10.1109/ASSCC.2011.6123605