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A 0.7V 810µW 10b 30MS/s comparator-based two-step pipelined ADC

TitleA 0.7V 810µW 10b 30MS/s comparator-based two-step pipelined ADC
Publication TypeConference Paper
Year of Publication2011
AuthorsLee, H-Y., D. Gubbins, B. Lee, and U. Moon
Conference NameIEEE Custom Integrated Circuits Conference - CICC
Pagination1 - 4
Date Published09/2011
PublisherIEEE
Conference LocationSan Jose, CA
ISBN Number978-1-4577-0222-8
Abstract

This paper presents a 10b 30MS/s comparator-based two-step pipelined ADC that uses a comparator instead of an opamp to reach low-voltage and low-power operation with a rail-to-rail input. This implementation also incorporates a digital offset calibration scheme in the comparator. The prototype ADC, fabricated in a 0.13μm CMOS process, consumes 810μW at 0.7V supply and achieves 121fJ FOM at 10MHz input frequency.

DOI10.1109/CICC.2011.6055326