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A 75dB SNDR, 10MHz conversion bandwidth stage-shared 2-2 MASH ΔΣ modulator dissipating 9mW

TitleA 75dB SNDR, 10MHz conversion bandwidth stage-shared 2-2 MASH ΔΣ modulator dissipating 9mW
Publication TypeConference Paper
Year of Publication2011
AuthorsZanbaghi, R., S. Saxena, G. C. Temes, and T. S. Fiez
Conference Name2011 IEEE Custom Integrated Circuits Conference (CICC)
Pagination1 - 4
Date Published10/2011
PublisherIEEE
Conference LocationSan Jose, CA
ISBN Number978-1-4577-0222-8
Keywordsmash, op-amp sharing, oversampling ratio, stage sharing, ΔΣ modulator
Abstract

This paper presents a new stage-sharing technique in a discrete-time 2-2 MASH ΔΣ ADC to reduce the modulator power consumption. The proposed technique shares all active blocks of the modulator second stage with its first stage. The 2-2 MASH modulator utilizes second-order Chain of Integrators with Weighted Feed-forward Summation (CIFF) and Cascade of Integrators with Distributed Feedback Branches (CIFB) architectures for the first and second stages, respectively. Using the proposed technique, the second integrator and the adder op-amps of the modulator first stage are shared with the first and second integrator op-amps of the second stage. Measurement results show that the modulator designed in a 0.13um CMOS technology achieves 75-dB SNDR over a 5MHz signal bandwidth with a clock frequency of 130MHz, while dissipating less than 9mW analog power.

DOI10.1109/CICC.2011.6055287