OREGON STATE UNIVERSITY

You are here

82 dB SNDR 20-channel incremental ADC with optimal decimation filter and digital correction

Title82 dB SNDR 20-channel incremental ADC with optimal decimation filter and digital correction
Publication TypeConference Paper
Year of Publication2010
AuthorsYu, W., M. Aslan, and G. C. Temes
Conference Name2010 IEEE Custom Integrated Circuits Conference - CICC
Pagination1 - 4
Date Published09/2010
PublisherIEEE
Conference LocationSan Jose, CA
ISBN Number978-1-4244-5758-8
Abstract

A third-order multi-channel incremental ADC with a 5-level quantizer is presented. An optimal decimation filter is used which minimizes the weighted sum of the thermal and quantization output noises. Digital correction is used to suppress mismatches in the multi-bit DAC. The prototype obtained a signal-to-noise-and-distortion ratio of 81.5 dB, within a total of 21.7 kHz signal bandwidth at a 10 MHz sampling frequency. The total power consumption for 20 channels is 6.7 mW.

DOI10.1109/CICC.2010.5617596