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Design techniques for discrete-time delta-sigma ADCs with extra loop delay

TitleDesign techniques for discrete-time delta-sigma ADCs with extra loop delay
Publication TypeConference Paper
Year of Publication2010
AuthorsWang, Y., and G. C. Temes
Conference NameProceedings of 2010 IEEE International Symposium on Circuits and Systems
Pagination2159 - 2162
Date Published06/2010
PublisherIEEE
Conference LocationParis, France
ISBN Number978-1-4244-5308-5
Abstract

In this paper, a general solution is proposed for the excess feedback loop delay issue for a discrete-time ΔΣ ADC. The corresponding low-distortion technique is also illustrated. Finally, the double-sampling ΔΣ ADC immune to the extra loop delay is described and verified through simulation.

DOI10.1109/ISCAS.2010.5537225