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A 2.5MHz BW and 78dB SNDR delta-sigma modulator using dynamically biased amplifiers

TitleA 2.5MHz BW and 78dB SNDR delta-sigma modulator using dynamically biased amplifiers
Publication TypeConference Paper
Year of Publication2008
AuthorsWang, Y., K. Lee, and G. C. Temes
Conference Name2008 IEEE Custom Integrated Circuits Conference
Pagination97 - 100
Date Published09/2008
PublisherIEEE
Conference LocationSan Jose, CA
ISBN Number978-1-4244-2018-6
Abstract

A new dynamically-biased scheme is proposed to implement a 13-bit delta-sigma modulator with a 2.5 MHz signal bandwidth. It uses the low-distortion architecture, and hence the opamp linearity requirements are greatly relaxed. Its noise-coupled and time-interleaved structure further decreases the power consumption. The prototype chip was fabricated in a 0.18 um CMOS technology. Experimental results show that 78 dB SNDR is achieved when it is clocked at 60 MHz sampling rate. With 1.6 V power supply, the power dissipation is 19.2 mW.

DOI10.1109/CICC.2008.4672030