A new dynamically-biased scheme is proposed to implement a 13-bit delta-sigma modulator with a 2.5 MHz signal bandwidth. It uses the low-distortion architecture, and hence the opamp linearity requirements are greatly relaxed. Its noise-coupled and time-interleaved structure further decreases the power consumption. The prototype chip was fabricated in a 0.18 um CMOS technology. Experimental results show that 78 dB SNDR is achieved when it is clocked at 60 MHz sampling rate. With 1.6 V power supply, the power dissipation is 19.2 mW.