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Closed-form expressions for modeling metal fill effects in interconnects

TitleClosed-form expressions for modeling metal fill effects in interconnects
Publication TypeConference Paper
Year of Publication2011
AuthorsShilimkar, V. S., S. G. Gaskill, and A. Weisshaar
Conference Name2011 IEEE 15th Workshop on Signal Propagation on Interconnects (SPI)
Pagination97 - 100
Date Published05/2011
PublisherIEEE
Conference LocationNaples, Italy
ISBN Number978-1-4577-0466-6
Abstract

This paper demonstrates efficient methods to account for parasitic capacitance and eddy-current loss in on-chip interconnects due to square metal fill. The parasitic capacitance extraction is based on an effective 3D to 2D reduction approach while the eddy-current loss in in-plane and out-of-plane metal fill is estimated by an empirical formula developed over a wide range of dimensions and frequencies. The interconnect capacitance matches with 3D electrostatic simulation and measurement within 2.1%. The additional parasitic resistance due to eddy-current loss in metal fill matches within 10% with 3D quasi-magnetostatic simulation results.

DOI10.1109/SPI.2011.5898849