Modern IC processes require metal fill patterning to achieve global uniformity of the metallization/oxide layers. Electrically these fills are often viewed as parasitics to be minimized. In this paper we actively use metal fill to suppress crosstalk noise between coupled traces by selectively grounding metal fills. However, the tradeoff of this improvement is higher total capacitance leading to increased interconnect delay times. We propose design rules that optimize this tradeoff between crosstalk and delay. The design parameters considered include placement of grounded fills, buffer distance and fill shapes. We show that it is best to start grounding metal fills farthest away from the signal traces.