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Frequency-Dependent Sampling Linearity

TitleFrequency-Dependent Sampling Linearity
Publication TypeJournal Article
Year of Publication2009
AuthorsBrown, T. W., M. Hakkarainen, and T. S. Fiez
JournalIEEE Transactions on Circuits and Systems I: Regular Papers
Pagination740 - 753
Date Published04/2009
Keywordsanalog–digital conversion, frequency response, harmonic distortion, nonlinear distortion, phase distortion, sample-and-hold circuits, Volterra series

A novel model predicts tracking nonlinearity (NL) in the form of harmonic distortion (HD) for weakly nonlinear (i.e., SFDR > 30 dBc) first-order open-loop sampling circuits. The mechanisms for the NL are exponential settling, amplitude modulation, phase modulation, and discrete-time modulation. The model demonstrates that HD typically increases at 20 dB per decade over most standard operating ranges and is a function of input frequency, sampling bandwidth, input amplitude, sample rate, and component NL. The application of the model is reduced to the equivalent of frequency-independent NL analysis over this range, requiring only a Taylor series expansion of the NL time constant. Design insight is given for common MOS switch types, revealing a high correlation between HD and bandwidth. The first method to quantify the tradeoff between thermal noise (SNR) and linearity [spurious-free dynamic range (SFDR)] for sampling circuits is presented. Measured HD ₂, HD ₃, HD ₄, and HD ₅ versus frequency at multiple sample rates of a sample-and-hold test chip fabricated in a 0.25-mum 1P5M CMOS process and Spectre simulation results support the findings. The results broadly apply to switched-capacitor circuits in general and sampling circuits specifically, regardless of technology.

Short TitleIEEE Trans. Circuits Syst. I