When the slewing and small-signal settling behavior of switched-capacitor integrators are explored properly, it becomes possible to obtain power optimal designs. However, in order to obtain robust designs with slewing behavior, the process variations have to be carefully considered. An analytical technique is developed to obtain power optimum design of switched-capacitor integrators with process variations consideration. The technique provides the worst and best ease estimates and obviates the need for Monte-Carlo simulations. We demonstrate the approach by providing performance variations of optimized integrators in a 0.6 μm CMOS process.