OREGON STATE UNIVERSITY

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A semi-synchronous SAR ADC

TitleA semi-synchronous SAR ADC
Publication TypeJournal Article
Year of Publication2012
AuthorsTong, T., P K. Hanumolu, and G. C. Temes
JournalAnalog Integrated Circuits and Signal Processing
Volume71
Issue3
Pagination407 - 410
Date Published06/2012
ISSN1573-1979
Keywordsdynamic clocking scheme, analog-to-digital converters, successive approximation conversion
Abstract

A semi-synchronous clocking scheme is proposed for successive approximation register (SAR) analog-to-digital converters (ADCs). The conversion time is dynamically allocated to the comparator decision and to the DAC settling in every bit cycle. This significantly improves the conversion speed.

DOI10.1007/s10470-011-9769-4
Short TitleAnalog Integr Circ Sig Process