SWIFT: A Low-Power Network-On-Chip Implementing the Token Flow Control Router Architecture With Swing-Reduced Interconnects

TitleSWIFT: A Low-Power Network-On-Chip Implementing the Token Flow Control Router Architecture With Swing-Reduced Interconnects
Publication TypeJournal Article
Year of Publication2012
AuthorsPostman, J., T. Krishna, C. Edmonds, L. - S. Peh, and P. Y. Chiang
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
VolumePP
Issue99
Pagination1 - 1
Date Published08/2012
ISSN1557-9999
Keywordsarchitecture, circuits, interconnect, low-power design, on-chip networks, routing
Abstract

A 64-bit, 8 ⨉ 8 mesh network-on-chip (NoC) is presented that uses both new architectural and circuit design techniques to improve on-chip network energy-efficiency, latency, and throughput. First, we propose token flow control, which enables bypassing of flit buffering in routers, thereby reducing buffer size and their power consumption. We also incorporate reduced-swing signaling in on-chip links and crossbars to minimize datapath interconnect energy. The 64-node NoC is experimentally validated with a 2 ⨉ 2 test chip in 90 nm, 1.2 V CMOS that incorporates traffic generators to emulate the traffic of the full network. Compared with a fully synthesized baseline 8 ⨉ 8 NoC architecture designed to meet the same peak throughput, the fabricated prototype reduces network latency by 20% under uniform random traffic, when both networks are run at their maximum operating frequencies. When operated at the same frequencies, the SWIFT NoC reduces network power by 38% and 25% at saturation and low loads, respectively.

DOI10.1109/TVLSI.2012.2211904
Short TitleIEEE Trans. VLSI Syst.