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A Single-Channel, 1.25-GS/s, 6-bit, 6.08-mW Asynchronous Successive-Approximation ADC With Improved Feedback Delay in 40-nm CMOS

TitleA Single-Channel, 1.25-GS/s, 6-bit, 6.08-mW Asynchronous Successive-Approximation ADC With Improved Feedback Delay in 40-nm CMOS
Publication TypeJournal Article
Year of Publication2012
AuthorsJiang, T., W. Liu, F. Y. Zhong, C. Zhong, K. Hu, and P. Y. Chiang
JournalIEEE Journal of Solid-State Circuits
Volume47
Issue10
Pagination2444 - 2453
Date Published10/2012
ISSN1558-173X
Keywordsanalog-to-digital converter (ADC), asynchronous logic, binary successive-approximation (SA) algorithm, single-channel ADC
Abstract

A single-channel, asynchronous successive-approximation (SA) ADC with improved feedback delay is fabricated in 40 nm CMOS. Compared with a conventional SAR structure that employs a single quantizer controlled by a digital feedback logic loop, the proposed SAR-ADC employs multiple quantizers for each conversion bit, clocked by an asynchronous ripple clock that is generated after each quantization. Hence, the sampling rate of the 6-bit ADC is limited only by the six delays of the Capacitive-DAC settling and each comparator's quantization delay, as the digital logic delay is eliminated. Measurement results of the 40 nm-CMOS SAR-ADC achieves a peak SNDR of 32.9 dB and 30.5 dB, at 1 GS/s and 1.25 GS/s, consuming 5.28 mW and 6.08 mW, leading to a FoM of 148 fJ/conv-step and 178 fJ/conv-step, respectively, in a core area less than 170 um by 85 um.

DOI10.1109/JSSC.2012.2204543
Short TitleIEEE J. Solid-State Circuits
Refereed DesignationRefereed