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Register file write data gating techniques and break-even analysis model

TitleRegister file write data gating techniques and break-even analysis model
Publication TypeConference Paper
Year of Publication2012
AuthorsDonkoh, E., T S. Ong, Y N. Too, and P. Y. Chiang
Conference NameProceedings of the 2012 ACM/IEEE international symposium on Low power electronics and design
Date Published08/2012
Conference LocationRedondo Beach, CA
ISBN Number978-1-4503-1249-3
Keywordsdata gating, low power, register file, sram

Register Files account for 30% of 32nm Intel WSM Core dynamic power of which 25% is due to write data distribution. We analyze Register File data gating strategies used to reduce write bitline dynamic power by as much as 96%. We explore the tradeoff of various data gating topologies (Global, Midway, Local), logic implementations (NAND, NOR, Tri-State), and techniques (Stack-Forcing, State-Forcing) to reduce both dynamic and leakage power. We then present a simple and accurate data gating break-even analysis model. The model comprehends "Data" and "Enable" switching activity, signal probability, logic implementation overhead, demonstrating an average error range of ±5%.