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An 80-dB DR, 7.2-MHz Bandwidth Single Opamp Biquad Based Delta Sigma Modulator Dissipating 13.7-mW

TitleAn 80-dB DR, 7.2-MHz Bandwidth Single Opamp Biquad Based Delta Sigma Modulator Dissipating 13.7-mW
Publication TypeJournal Article
Year of Publication2013
AuthorsZanbaghi, R., P K. Hanumolu, and T. S. Fiez
JournalIEEE Journal of Solid-State Circuits
Volume48
Issue2
Pagination487 - 501
Date Published02/2013
ISSN1558-173X
Abstract

A novel low power compact loop filter using a single amplifier biquad (SAB) network is presented for continuous-time (CT) delta-sigma (ΔΣ) modulators. This new technique reduces power consumption and die area by minimizing the number of active elements and simplifying the modulator topology. The new SAB network has a transfer function (TF) zero, which implements a local feedforward (FF) path in system-level diagram. By having a local FF branch embedded in the SAB network, the FF branches to the summing block in the SAB based feedforward modulator topology is reduced to half the number of FF branches in the conventional topology. Consequently, the SAB based modulator utilizes a switch-capacitor (SC) adder replacing the commonly used CT adder and the sample & hold blocks in the conventional architecture. The SAB based loop filter with reduced FF branches simplifies the design and implementation of the high-order continuous-time ΔΣ modulator. The proposed loop filter is a general filter, which can be used for both high and low oversampling ratios (OSRs). A 4th-order low pass continuous-time ΔΣ modulator is designed and implemented in 130 nm process to confirm the effectiveness of the proposed techniques. Within a 7.2 MHz signal bandwidth, the measured dynamic range and SFDR of this prototype IC are 80 dB and 83.1 dB, respectively, and the total power consumption of 13.7 mW.

DOI10.1109/JSSC.2012.2221194
Short TitleIEEE J. Solid-State Circuits