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A 75-dB SNDR, 5-MHz Bandwidth Stage-Shared 2-2 MASH ΔΣ Modulator Dissipating 16 mW Power

TitleA 75-dB SNDR, 5-MHz Bandwidth Stage-Shared 2-2 MASH ΔΣ Modulator Dissipating 16 mW Power
Publication TypeJournal Article
Year of Publication2012
AuthorsZanbaghi, R., S. Saxena, G. C. Temes, and T. S. Fiez
JournalIEEE Transactions on Circuits and Systems I: Regular Papers
Volume59
Issue8
Pagination1614 - 1625
Date Published08/2012
ISSN1558-0806
Keywordsbiquad filter, continuous-time, delta-sigma modulator, oversampling ratio, single op-amp based filter
Abstract

This paper presents a new stage-sharing technique in a discrete-time (DT) 2-2 MASH delta-sigma (ΔΣ) ADC to reduce the modulator power consumption and chip die area. The proposed technique shares all active blocks between the two stages of the modulator. The 2-2 MASH modulator utilizes the second-order Chain of Integrators with Weighted Feed-forward Summation (CIFF) and the Cascade of Integrators with Distributed Feedback Branches (CIFB) architectures for the first and second stages, respectively. Using the proposed technique, the second integrator and the adder op-amps of the modulator first stage are shared with the first and second integrator op-amps of the second stage. In addition to the stage-sharing scheme, other changes are introduced to improve the modulator dynamic range (DR) and power dissipation. Measurement results show that the modulator designed in a 0.13 μm CMOS technology achieves 75 dB SNDR over a 5 MHz signal bandwidth with a clock frequency of 130 MHz, while dissipating less than 9 mW analog power.

DOI10.1109/TCSI.2012.2206509
Short TitleIEEE Trans. Circuits Syst. I