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Correlated jitter sampling for jitter cancellation in pipelined TDC

TitleCorrelated jitter sampling for jitter cancellation in pipelined TDC
Publication TypeConference Paper
Year of Publication2012
AuthorsOh, T., H. Venkatram, J. Guerber, and U. Moon
Conference NameIEEE International Symposium on Circuits and Systems - ISCAS 2012
Pagination810 - 813
Date Published05/2012
Conference LocationSeoul, Korea (South)
ISBN Number978-1-4673-0217-3

In this paper, the Correlated Jitter Sampling (CJS) technique, which alleviates the jitter induced error from the time reference in pipelined Time-to-Digital Converter (TDC), is proposed. The auxiliary pipelined TDC is employed to remove the jitter induced error of the main pipelined TDC in the CJS technique. A 12b pipelined TDC adopting the CJS technique in the 1st time quantization stage is simulated to validate the proposed technique. Simulation results show that the TDC can achieve a flat SNDR performance of 70dB regardless of the jitter from time reference up to 25% jitter of 1TLSB in reference clock, which is the maximum error allowed within a designed redundancy range of the pipelined TDC.