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A linearized, low-phase-noise VCO-based 25-GHz PLL with autonomic biasing

TitleA linearized, low-phase-noise VCO-based 25-GHz PLL with autonomic biasing
Publication TypeJournal Article
Year of Publication2013
AuthorsSadhu, B., M. A. Ferriss, A. Natarajan, S. Yaldiz, J-O. Plouchart, A. Rylyakov, A. Valdes-Garcia, B. D. Parker, A. Babakhani, S. Reynolds, X. Li, L. Pileggi, R. Harjani, J. Tierno, and D. Friedman
JournalIEEE Journal of Solid-State Circuits
Pagination1138 - 1150
Date Published05/2013

This paper describes a new approach to low-phasenoise LC VCO design based on transconductance linearization of the active devices. A prototype 25 GHz VCO based on this linearization approach is integrated in a dual-path PLL and achieves superior performance compared to the state of the art. The design is implemented in 32 nm SOI CMOS technology and achieves a phase noise of - 130 dBc/Hz at a 10 MHz offset from a 22 GHz carrier. Additionally, the paper introduces a new layout approach for switched capacitor arrays that enables a wide tuning range of 23%. More than 1500 measurements of the PLL across PVT variations were taken, further validating the proposed design. Phase noise variation across 55 dies for four different frequencies is σ < 0.6 dB. Also, phase noise variation across supply voltages of 0.7-1.5 V is 2 dB and across 60 °C temperature variation is 3 dB. At the 25 GHz center frequency, the VCO FOMT is 188 dBc/Hz. Additionally, a digitally assisted autonomic biasing technique is implemented in the PLL to provide a phase noise and power optimized VCO bias across frequency and process. Measurement results indicate the efficacy of the autonomic biasing scheme.

Short TitleIEEE J. Solid-State Circuits